NORCHIP 2012最新文献_第5页

Wideband Reconfigurable Capacitive shunt-feedback LNA in 65nm CMOS 65nm CMOS的宽带可重构电容并联反馈LNA

NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403126

I. Din, J. Wernehag, S. Andersson, S. Mattisson

引用次数: 3

Nanoscale CMOS impulse radar - from research to product 纳米级CMOS脉冲雷达-从研究到产品

NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403132

D. Wisland

{"title":"Nanoscale CMOS impulse radar - from research to product","authors":"D. Wisland","doi":"10.1109/NORCHP.2012.6403132","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403132","url":null,"abstract":"Summary form only given. CMOS Ultra Wideband radar technology gives rise to several new and emerging sensor applications ranging from industrial proximity sensors to advanced medical sensors detecting heart movement and breathing. The ability to see through objects combined with the high processing speed and low energy consumption inherent in nanometer CMOS makes this technology a very competitive approach compared to other sensor technologies like optical, ultrasound and X-ray. Ultra Wideband impulse radars are however in general hard to implement in standard CMOS technology due to the strict requirements on the front-end A/D converter in terms of a multi-GHz conversion rate combined with a high dynamic range. A very high sampling rate is required to achieve sufficient time-domain resolution converting into spatial resolution of the radar system. This talk will focus on an alternative impulse radar architecture utilizing 1-bit A/D conversion moving the processing challenge from the amplitude domain to the time domain. The technique is referred to as Continuous-Time Binary Value (CTBV) and will be the main topic of this presentation which will in particular focus on the utilization of continuous-time signal processing to enhance spatial resolution and conserve energy followed by the main challenges and opportunities related to a full CMOS implementation of the system. The theory will be exemplified with industrial products from Novelda taking advantage of the CTBV technique. In addition different applications and real-life case-studies will be presented along with recent R&D progress within the area.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125226468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Performability of error control schemes for NOC interconnects NOC互连错误控制方案的可执行性

NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403123

Deena M. Zamzam, Mohamed A. Abd El-Ghany, K. Hofmann

引用次数: 6

Architectural trends in GHz speed DACs GHz速度dac的架构趋势

NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403097

S. Balasubramanian, W. Khalil

引用次数: 7

Novel SRAM bias control circuits for a low power L1 data cache 用于低功耗L1数据缓存的新型SRAM偏置控制电路

NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403113

A. Seyedi, Adrià Armejach, A. Cristal, O. Unsal, M. Valero

{"title":"Novel SRAM bias control circuits for a low power L1 data cache","authors":"A. Seyedi, Adrià Armejach, A. Cristal, O. Unsal, M. Valero","doi":"10.1109/NORCHP.2012.6403113","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403113","url":null,"abstract":"This paper proposes two novel bias control circuits to manage the power consumption of inactive cache cells in data retention mode. Both circuits have lower power consumption and area overheads when compared to previous proposals. The first proposed circuit (Dynamic Bias Control circuit or DB-Control circuit) dynamically tracks the reference current and sets the bias voltage of cells, while the second (Self-Adjust Bias Control circuit or SAB-Control circuit) has a self-adjust property to set the bias voltages and also alleviates the instability problems that appear due to noise injection. Although any SRAM array can benefit from these circuits, to show their usefulness, we frame our study on a recently proposed dual-versioning L1 data cache that has been designed for chip multi-processors that implement optimistic concurrency proposals, where leakage current has more effect on power dissipation and on circuit instability. Therefore, we add the proposed bias control circuits to a 32KB dual-versioning SRAM (dvSRAM) cache and simulate and optimize the entire cache with 45-nm CMOS technology at 2GHz processor frequency and 1V supply voltage. The simulations demonstrate the effectiveness of our proposed circuits to reduce the energy consumption of dvSRAM L1 data cache by 35.8% on average compared to the typical dvSRAM cache. This is achieved with a modest area increase of 1.6% per sub-array and negligible delay overhead. We also show that instability problems are alleviated by using the SAB-Control circuit.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"61 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130281268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Intermediate nodes selection schemes for Network Coding in Network-on-Chips 片上网络中网络编码的中间节点选择方案

NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403130

A. Shalaby, Mohamed El-Sayed Ragab, V. Goulart

引用次数: 3

Analyses of single-stage complementary self-biased CMOS differential amplifiers 单级互补自偏CMOS差分放大器分析

NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403115

V. Milovanovic, H. Zimmermann

引用次数: 5

Wideband RF detector design for high performance on-chip test 用于高性能片上测试的宽带射频检测器设计

NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403140

Quoc-Tai Duong, J. Dabrowski

引用次数: 3

Linearization of RF power amplifiers using an enhanced memory polynomial predistorter 利用增强型记忆多项式预失真器实现射频功率放大器的线性化

NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403124

F. Tafuri, C. Guaragnella, M. Fiore, T. Larsen

引用次数: 11

Modeling and design of a dual-residue pipelined ADC in 130nm CMOS 130nm CMOS双残基流水线ADC的建模与设计

NORCHIP 2012 Pub Date : 2012-11-01 DOI: 10.1109/NORCHP.2012.6403104

Eirik Steen-Hansen, T. Ytterdal

{"title":"Modeling and design of a dual-residue pipelined ADC in 130nm CMOS","authors":"Eirik Steen-Hansen, T. Ytterdal","doi":"10.1109/NORCHP.2012.6403104","DOIUrl":"https://doi.org/10.1109/NORCHP.2012.6403104","url":null,"abstract":"A 9-bit 50MS/s dual-residue pipelined ADC is modeled and analyzed. The first stage is a modified pipelined ADC stage, while the other stages use an interpolator to resolve the signal; the focus is on designing these stages. A new successive approximation based interpolator (SAI) is proposed. This interpolator is insensitive to parasitic capacitances, and makes it possible to utilize open loop residue amplifiers. The dual-residue architecture is insensitive to the gain of the residue amplifiers, and only a matching between two amplifiers is necessary. Limiting parameters of the ADC are the offset in the residue amplifiers, as well as gain mismatch between the amplifiers. The ADC with the SAI got an ENOB of 8.99-bit when simulated without offset and gain mismatch. The maximum allowed offset voltage of the residue amplifier is equation, and with this offset voltage for all the amplifiers in the ADC the ENOB dropped to 8.61-bit. The maximum allowable mismatch between the two residue amplifiers is equation, with this mismatch the ENOB is 8.85-bit. Both these demands should be possible to reach without the use of calibration. With a zero-crossing based amplifier the last 8 stages of the ADC has an estimated power consumption of 2.1mW.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115998453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0