Performability of error control schemes for NOC interconnects

Abstract

High Reliability against noise, high performance and low energy consumption are major challenges facing Network on Chip (NoC). The effect of high reliable and efficient forward error correction schemes is analyzed. Interconnect Performability is introduced as a unified measure of performance and reliability. A detailed comparative analysis of different forward error correction schemes is presented using performability analytical models taking into consideration voltage swing and the impact of noise power. The results showed the proposed code Self-correction Syndrome Scheme achieved better performability by 25% and capable of achieving better performability for larger noise power.