{"title":"GHz速度dac的架构趋势","authors":"S. Balasubramanian, W. Khalil","doi":"10.1109/NORCHP.2012.6403097","DOIUrl":null,"url":null,"abstract":"Recent interests from the research community in building digitized transmitters has led to numerous architectural and circuit-level developments in the design of digital-to-analog converters (DACs) in the GHz space. Several challenges exist in terms of interface overhead and process capabilities that fundamentally influence the achievable speed and performance numbers. This paper aims to provide the reader with some of the emerging architectural innovations that address these challenges and aid in the transition of DACs into the GHz regime.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Architectural trends in GHz speed DACs\",\"authors\":\"S. Balasubramanian, W. Khalil\",\"doi\":\"10.1109/NORCHP.2012.6403097\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Recent interests from the research community in building digitized transmitters has led to numerous architectural and circuit-level developments in the design of digital-to-analog converters (DACs) in the GHz space. Several challenges exist in terms of interface overhead and process capabilities that fundamentally influence the achievable speed and performance numbers. This paper aims to provide the reader with some of the emerging architectural innovations that address these challenges and aid in the transition of DACs into the GHz regime.\",\"PeriodicalId\":332731,\"journal\":{\"name\":\"NORCHIP 2012\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"NORCHIP 2012\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NORCHP.2012.6403097\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"NORCHIP 2012","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NORCHP.2012.6403097","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Recent interests from the research community in building digitized transmitters has led to numerous architectural and circuit-level developments in the design of digital-to-analog converters (DACs) in the GHz space. Several challenges exist in terms of interface overhead and process capabilities that fundamentally influence the achievable speed and performance numbers. This paper aims to provide the reader with some of the emerging architectural innovations that address these challenges and aid in the transition of DACs into the GHz regime.
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