R. Ubar, Viljar Indus, Oliver Kalmend, T. Evartson, E. Orasson
{"title":"Functional Built-In Self-Test for processor cores in SoC","authors":"R. Ubar, Viljar Indus, Oliver Kalmend, T. Evartson, E. Orasson","doi":"10.1109/NORCHP.2012.6403148","DOIUrl":null,"url":null,"abstract":"A methodology for organization of at-speed functional Built-In Self-Test in processors, based on real functional routines is presented. The proposed self-test includes on-chip test application and response collection by using the functionality of the processor under test. We use divide-and-conquer approach. At component level, tests are targeting faults in components. At processor level, the functionality of the processor is used to apply functional test patterns to each component at-speed. Differently from usual Built-in Self-Test schemes, the test patterns are not needed to store in the chip under test, they will be generated on-line by the resources of the system.","PeriodicalId":332731,"journal":{"name":"NORCHIP 2012","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"NORCHIP 2012","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NORCHP.2012.6403148","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A methodology for organization of at-speed functional Built-In Self-Test in processors, based on real functional routines is presented. The proposed self-test includes on-chip test application and response collection by using the functionality of the processor under test. We use divide-and-conquer approach. At component level, tests are targeting faults in components. At processor level, the functionality of the processor is used to apply functional test patterns to each component at-speed. Differently from usual Built-in Self-Test schemes, the test patterns are not needed to store in the chip under test, they will be generated on-line by the resources of the system.