Testing of an off-chip NoC protocol using a BIST/Synthesizable Testbench approach

Abstract

To make systems infinitely scalable is the holy grail of chip design and crux that needs to be solved in order to invent a sustainable design methodology. Network-on-Chip (NoC) has been suggested as this solution as it replaces the traditional buses for on-chip interconnection purposes. However, to reach infinite scalability, off-chip extensions to the NoC protocols are needed in order to maintain scalability at an affordable cost of manufacturability. Going off-chip introduces more levels of complexity when it comes to testing, not only should the chip testing be speedy, the off-chip connections must also be testable in a fast manner, the fastest way being a set of BISTs testing the whole structure in parallel. In this paper, we present a BIST approach for testing an off-chip NoC protocol used in a 4×4 Network-on-Chip configuration. It has 16 processor-nodes implemented on four interconnected plesiochronous Altera Stratix-II FPGA boards, each board hosting a Quad-core NoC.