通孔可配置晶体管阵列结构的光刻分析

NORCHIP 2012 Pub Date : 2012-11-01 DOI:10.1109/NORCHP.2012.6403145

V. D. Bem, A. Reis, R. Ribas

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引用次数: 2

摘要

常规织物有望减轻制造工艺的变化，提高深亚微米CMOS技术的制造成品率。本文对基于晶体管阵列的规则织物的光刻性能进行了广泛的分析。通过光刻模拟对文献中提出的四种不同方法(VCC, INVA, VCLB和VCTA)进行了评估。边缘放置误差(EPE)作为光刻性能度量被考虑在内。

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Lithography analysis of via-configurable transistor-array fabrics

Regular fabrics are expected to mitigate manufacturing process variations, increasing the fabrication yield in deep sub-micron CMOS technologies. This paper presents an extensive analysis of lithography behaviour of transistor-array based regular fabrics. Four different approaches presented in the literature (VCC, INVA, VCLB and VCTA) have been evaluated through lithography simulations. The well-established concept of edge placement error (EPE) has been taken into account as lithography behavior metric.

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来源期刊

NORCHIP 2012

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