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2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)最新文献

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A 100kHz-Bandwidth 98.3dB-SNDR Noise-Shaping SAR ADC with Improved Mismatch Error Shaping and Speed-Up Techniques 一种100khz带宽98.3dB-SNDR噪声整形SAR ADC，具有改进的失配误差整形和加速技术
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830166
Kazunori Hasebe, Shinichirou Etou, D. Miyazaki, Taiki Iguchi, Yuki Yagishita, Mika Takasaki, Takeru Nogamida, Hiroyuki Watanabe, T. Matsumoto, Y. Katayama
{"title":"A 100kHz-Bandwidth 98.3dB-SNDR Noise-Shaping SAR ADC with Improved Mismatch Error Shaping and Speed-Up Techniques","authors":"Kazunori Hasebe, Shinichirou Etou, D. Miyazaki, Taiki Iguchi, Yuki Yagishita, Mika Takasaki, Takeru Nogamida, Hiroyuki Watanabe, T. Matsumoto, Y. Katayama","doi":"10.1109/vlsitechnologyandcir46769.2022.9830166","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830166","url":null,"abstract":"Noise-Shaping (NS) SAR ADCs can have high Dynamic Range (DR) and be easily adopted to IoT, audio and many other applications. This paper proposes four techniques to improve the DR and conversion speed of NS SAR ADCs. A prototype NS SAR ADC achieves SNDR/SNR/SFDR of 98.3dB/99.3dB/108.5dB with 100kHz bandwidth and 12.8MS/s. Schreier FoM reaches 175.3dB.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126434729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 30GHz-BW < -57dB-IM3 Direct RF Receiver Analog Front End in 16nm FinFET 30GHz-BW < -57dB-IM3的16nm FinFET直接射频接收器模拟前端
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830293
A. Ramkaj, Adalberto Cantoni, G. Manganaro, S. Devarajan, M. Steyaert, F. Tavernier
{"title":"A 30GHz-BW < -57dB-IM3 Direct RF Receiver Analog Front End in 16nm FinFET","authors":"A. Ramkaj, Adalberto Cantoni, G. Manganaro, S. Devarajan, M. Steyaert, F. Tavernier","doi":"10.1109/vlsitechnologyandcir46769.2022.9830293","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830293","url":null,"abstract":"This paper presents a 30GHz-bandwidth analog front end for a direct RF receiver, featuring a multi-segment LC filter with distributed 0-11dB variable attenuation, and a new push-pull source-degenerated hybrid amplifier followed by a push-pull cascoded buffer. Implemented in 16nm FinFET, the prototype front end achieves < -57dB-IM3 and supports 2048-QAM with < 1.6%/< -48dB EVM/ACLR in its entire band while consuming 210mW, demonstrating beyond state-of-the-art performance.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131362764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
8-Layer 3D Vertical Ru/AlOxNy/TiN RRAM with Mega-Ω Level LRS for Low Power and Ultrahigh-density Memory 8层3D垂直Ru/AlOxNy/TiN RRAM与Mega-Ω级LRS低功耗和超高密度存储器
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830164
S. Qin, Maryann C. Tung, Emma Belliveau, Shuhan Liu, Jimin Kwon, Wei-Chen Chen, Zizhen Jiang, S. Wong, H. P. Wong
{"title":"8-Layer 3D Vertical Ru/AlOxNy/TiN RRAM with Mega-Ω Level LRS for Low Power and Ultrahigh-density Memory","authors":"S. Qin, Maryann C. Tung, Emma Belliveau, Shuhan Liu, Jimin Kwon, Wei-Chen Chen, Zizhen Jiang, S. Wong, H. P. Wong","doi":"10.1109/vlsitechnologyandcir46769.2022.9830164","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830164","url":null,"abstract":"We present an 8-layer 3D vertical Ru/AlOxNy/TiN RRAM device integrated with a transistor as current driver at the end of the vertical pillar. This RRAM cell is designed for low power and ultrahigh-density non-volatile memory: 1) a large low-resistance state (LRS) value of around 1 MΩ with an ON/OFF window of > 102 to ensure successful write/read operations for the worst-case cell in the array; 2) a thin (15 nm) Ru word-plane (WP) electrode to reduce parasitic resistance yet scalable vertically to > 128 layers; 3) 2-bit-per-cell capability that doubles the memory capacity. A 128-layer 3D vertical RRAM with Ru/AlOxNy/TiN can achieve bit density of 29.5 Gb/mm2 with 2 bits per cell and CMOS under Array (CuA), based on simulations that include leakage current, pillar, and WP resistances. Reliability tests show the RRAM cell can be reliably switched up to 3×106 write/read cycles and maintain stable resistance states > 104 s at 85 °C.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134572862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Shared-Inductor Structure-Reconfigurable Regulating Rectifier (SR-RR) Enabling 6.78-MHz AC-DC Rectification and 1-MHz DC-DC Energy Recycling 共享电感结构可重构调节整流器(SR-RR)实现6.78 mhz AC-DC整流和1mhz DC-DC能量回收
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830263
Fu-Bin Yang, Dao-Han Yao, Po-Hung Chen
{"title":"A Shared-Inductor Structure-Reconfigurable Regulating Rectifier (SR-RR) Enabling 6.78-MHz AC-DC Rectification and 1-MHz DC-DC Energy Recycling","authors":"Fu-Bin Yang, Dao-Han Yao, Po-Hung Chen","doi":"10.1109/vlsitechnologyandcir46769.2022.9830263","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830263","url":null,"abstract":"This paper presents a 6.78-MHz quad-mode structure-reconfigurable regulating rectifier (SR-RR) for wireless power transfer (WPT) systems. The proposed SR-RR combines AC-DC regulating rectifier and DC-DC boost converter functions in one stage by sharing a receiver coil and power switches. The measurement results demonstrate 91.9% peak receiver efficiency and 64.4% peak system efficiency while obtaining 38.9% light-load efficiency improvement and 1.7X output power extension.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131491477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
From System-on-Chip (SoC) to System on Multi-Chip (SoMC) architectures: Scaling integrated systems beyond the limitations of deep-submicron single chip technologies 从片上系统(SoC)到多片上系统(SoMC)架构:扩展集成系统，超越深亚微米单芯片技术的限制
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830253
Christopher Patrick, S. C. Song, I. Khan, Nader Nikfar, M. Severson, Shree Pandey, Matt Kaiser, Manav Shah, Pat Lawlor, Deb Marich, Carina Affinito, Rajeev Jain
{"title":"From System-on-Chip (SoC) to System on Multi-Chip (SoMC) architectures: Scaling integrated systems beyond the limitations of deep-submicron single chip technologies","authors":"Christopher Patrick, S. C. Song, I. Khan, Nader Nikfar, M. Severson, Shree Pandey, Matt Kaiser, Manav Shah, Pat Lawlor, Deb Marich, Carina Affinito, Rajeev Jain","doi":"10.1109/vlsitechnologyandcir46769.2022.9830253","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830253","url":null,"abstract":"The mobile wireless revolution has relied on IP integration platforms and processes that allows rapid innovation and integration of new IP such as 5G, while achieving low power and low cost by quickly leveraging new technology nodes. Complex systems have been integrated into SoCs and enhanced every year as technology shrinks. However, current trends in SOCs for diverse markets like mobile, compute, automotive, and AI servers will lead to impractical die sizes due to reduction in the rate of area shrinkage with future deep sub-micron technology nodes. Partitioning the SoC into multiple die (also called chiplets) in a multi-chip configuration may help, but this also brings new challenges in architecture design, thermal, power distribution network, die-to-die interface design, and chip design flow. These challenges are highlighted in this paper.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132641735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improving the SiGeAsTe Ovonic Threshold Switching (OTS) Characteristics by Microwave Annealing for Excellent Endurance (> 1011) and Low Drift Characteristics 利用微波退火技术改善SiGeAsTe卵泡阈值开关(OTS)特性，使其具有优异的续航时间(> 1011)和低漂移特性
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830179
J. Lee, S. Kim, Sangmin Lee, Sanghyun Ban, Seongjae Heo, Donghwa Lee, O. Mosendz, H. Hwang
{"title":"Improving the SiGeAsTe Ovonic Threshold Switching (OTS) Characteristics by Microwave Annealing for Excellent Endurance (> 1011) and Low Drift Characteristics","authors":"J. Lee, S. Kim, Sangmin Lee, Sanghyun Ban, Seongjae Heo, Donghwa Lee, O. Mosendz, H. Hwang","doi":"10.1109/vlsitechnologyandcir46769.2022.9830179","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830179","url":null,"abstract":"To improve the reliability of a nanoscale (d=30 nm) ovonic threshold switching (OTS) selector, we report for the first time the effect of microwave annealing (MWA) on the electrical characteristics of an OTS device. The MWA-treated OTS device shows low initial forming voltage, excellent endurance (> 1011), and reduced threshold voltage (Vth) drift (~ 67 %), while maintaining its great switching characteristics (Ioff = 0.8 nA at 1.1 V). Enhanced As-Te bonding probability after MWA, which was confirmed by Raman spectroscopy and density functional theory (DFT) calculations, can explain low forming voltage and improved device reliability.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130834816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 9.8-fJ/conv.-step FoMW 8b 2.5-GS/s Single-Channel CDAC-Assisted Subranging ADC with Reference-Embedded Comparators fj / conv 9.8。-step formw8b 2.5-GS/s单通道cdac辅助子量程ADC与参考嵌入式比较器
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830239
Jia-Ching Wang, Bing-Yang Li, T. Kuo
{"title":"A 9.8-fJ/conv.-step FoMW 8b 2.5-GS/s Single-Channel CDAC-Assisted Subranging ADC with Reference-Embedded Comparators","authors":"Jia-Ching Wang, Bing-Yang Li, T. Kuo","doi":"10.1109/vlsitechnologyandcir46769.2022.9830239","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830239","url":null,"abstract":"This paper presents an 8b 2.5-GS/s single-channel CDAC-assisted three-stage subranging ADC using reference-embedded comparators (RECs). In this work, both the power consumption and calibration overhead of the RECs are largely reduced by a simple capacitor DAC (CDAC) designed for this subranging ADC. In addition, the severe CDAC gain error is also largely reduced by a simple gain error compensation design, which is not only insensitive to the PVT variation but is also a low-complexity design. This ADC is implemented in 28-nm CMOS technology and occupies an active area of 0.024 mm2. With a Nyquist-rate input at 2.5 GS/s, the measured SNDR is 44.8 dB with a 3.5-mW power consumption only. This ADC achieves a Walden Figure-of-Merits of 9.8 fJ/conv.-step only. Compared to the single-channel prior-art ADCs with a sampling rate ≥1.5 GS/s and a resolution of 6-10b, this work advances the state-of-the-art by nearly 2×.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133666692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Computing-in-Memory with SuperFlash® memBrain™ Technology 使用SuperFlash®memBrain™技术进行内存计算
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830145
Nhan Do, H. Tran, M. Reiten
{"title":"Computing-in-Memory with SuperFlash® memBrain™ Technology","authors":"Nhan Do, H. Tran, M. Reiten","doi":"10.1109/vlsitechnologyandcir46769.2022.9830145","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830145","url":null,"abstract":"The concept and experimental result of using SuperFlash® based neuromorphic memory to solve the data communication bottlenecks in neural network edge devices are discussed. The implementation of a 2Mb memory array as an analog vector matrix multiplier (VMM) in a 28 nm SuperFlash® eFlash (ESF3-28 nm) process together with design concepts, weight tuning technique, performance factors, and reliability, are also presented in detail.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124094018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
First Si-Waveguide-Integrated InGaAs/InAlAs Avalanche Photodiodes on SOI Platform SOI平台上首款硅波导集成InGaAs/InAlAs雪崩光电二极管
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830481
Jishen Zhang, Haiwen Xu, K. Tan, S. Wicaksono, Qiwen Kong, Gong Zhang, Yue Chen, Chen Sun, Haibo Wang, Chao Wang, Zijie Zheng, Leming Jiao, Zuopu Zhou, C. Lim, S. Yoon, Xiao Gong
{"title":"First Si-Waveguide-Integrated InGaAs/InAlAs Avalanche Photodiodes on SOI Platform","authors":"Jishen Zhang, Haiwen Xu, K. Tan, S. Wicaksono, Qiwen Kong, Gong Zhang, Yue Chen, Chen Sun, Haibo Wang, Chao Wang, Zijie Zheng, Leming Jiao, Zuopu Zhou, C. Lim, S. Yoon, Xiao Gong","doi":"10.1109/vlsitechnologyandcir46769.2022.9830481","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830481","url":null,"abstract":"For the first time, a novel Si-waveguide-integrated InGaAs/InAlAs avalanche photodiode (APD) on the SOI platform was realized, in which light propagating along the Si waveguide is evanescently absorbed by an overlaying InGaAs layer bonded on it. The integrated-APD exhibits a high responsivity of 0.99 A/W at 1570 nm, a dark current (Idark) of 7.6 nA at 90% breakdown voltage (Vbr), and a maximum gain of larger than 70. The good quality of the bonded III-V epi-layers and promising performance of the fabricated waveguide-integrated APDs has been realized where the negligible variation induced by the bonding process has been confirmed.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123424830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
VLSI Technology and Circuits 2022 Cover Page VLSI技术和电路2022封面页
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830342
{"title":"VLSI Technology and Circuits 2022 Cover Page","authors":"","doi":"10.1109/vlsitechnologyandcir46769.2022.9830342","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830342","url":null,"abstract":"","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122007207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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