{"title":"A 9.8-fJ/conv.-step FoMW 8b 2.5-GS/s Single-Channel CDAC-Assisted Subranging ADC with Reference-Embedded Comparators","authors":"Jia-Ching Wang, Bing-Yang Li, T. Kuo","doi":"10.1109/vlsitechnologyandcir46769.2022.9830239","DOIUrl":null,"url":null,"abstract":"This paper presents an 8b 2.5-GS/s single-channel CDAC-assisted three-stage subranging ADC using reference-embedded comparators (RECs). In this work, both the power consumption and calibration overhead of the RECs are largely reduced by a simple capacitor DAC (CDAC) designed for this subranging ADC. In addition, the severe CDAC gain error is also largely reduced by a simple gain error compensation design, which is not only insensitive to the PVT variation but is also a low-complexity design. This ADC is implemented in 28-nm CMOS technology and occupies an active area of 0.024 mm2. With a Nyquist-rate input at 2.5 GS/s, the measured SNDR is 44.8 dB with a 3.5-mW power consumption only. This ADC achieves a Walden Figure-of-Merits of 9.8 fJ/conv.-step only. Compared to the single-channel prior-art ADCs with a sampling rate ≥1.5 GS/s and a resolution of 6-10b, this work advances the state-of-the-art by nearly 2×.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830239","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This paper presents an 8b 2.5-GS/s single-channel CDAC-assisted three-stage subranging ADC using reference-embedded comparators (RECs). In this work, both the power consumption and calibration overhead of the RECs are largely reduced by a simple capacitor DAC (CDAC) designed for this subranging ADC. In addition, the severe CDAC gain error is also largely reduced by a simple gain error compensation design, which is not only insensitive to the PVT variation but is also a low-complexity design. This ADC is implemented in 28-nm CMOS technology and occupies an active area of 0.024 mm2. With a Nyquist-rate input at 2.5 GS/s, the measured SNDR is 44.8 dB with a 3.5-mW power consumption only. This ADC achieves a Walden Figure-of-Merits of 9.8 fJ/conv.-step only. Compared to the single-channel prior-art ADCs with a sampling rate ≥1.5 GS/s and a resolution of 6-10b, this work advances the state-of-the-art by nearly 2×.