From System-on-Chip (SoC) to System on Multi-Chip (SoMC) architectures: Scaling integrated systems beyond the limitations of deep-submicron single chip technologies

Abstract

The mobile wireless revolution has relied on IP integration platforms and processes that allows rapid innovation and integration of new IP such as 5G, while achieving low power and low cost by quickly leveraging new technology nodes. Complex systems have been integrated into SoCs and enhanced every year as technology shrinks. However, current trends in SOCs for diverse markets like mobile, compute, automotive, and AI servers will lead to impractical die sizes due to reduction in the rate of area shrinkage with future deep sub-micron technology nodes. Partitioning the SoC into multiple die (also called chiplets) in a multi-chip configuration may help, but this also brings new challenges in architecture design, thermal, power distribution network, die-to-die interface design, and chip design flow. These challenges are highlighted in this paper.