2010 International Conference on Simulation of Semiconductor Processes and Devices最新文献_第2页

Improvement of the interface integrity between a high-k dielectric film and a metal gate electrode by controlling point defects and residual stress 通过控制点缺陷和残余应力提高高k介电膜与金属栅极之间的界面完整性

2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604526

Ken Suzuki, Tatsuya Inoue, H. Miura

{"title":"Improvement of the interface integrity between a high-k dielectric film and a metal gate electrode by controlling point defects and residual stress","authors":"Ken Suzuki, Tatsuya Inoue, H. Miura","doi":"10.1109/SISPAD.2010.5604526","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604526","url":null,"abstract":"In this study, the influence of composition of thin films on the interface integrity between a hafnium dioxide thin film and a gate electrode was investigated by using a quantum chemical molecular dynamics method. Effect of the fluctuation of the composition around the HfO2±x/metal interface on the formation of the interfacial layer was analyzed quantitatively. Post-oxidation annealing after deposition of the hafnium oxide film restored oxygen vacancies and removed carbon interstitials from the film and thus, improved the quality of the oxide. However, when the excessive interstitial oxygen atoms remained in the film, the quality of the interface was deteriorated by forming a new interfacial oxide layer between the hafnium oxide and the deposited metal such as tungsten. No interfacial layer was observed, however, when a gold thin film was deposited on the hafnium oxide film with the various defects. Therefore, it is very important to control the composition around the interface, i.e., to minimize those point defects in the hafnium dioxide films and/or to introduce a diffusion barrier layer onto the oxide for improving the electronic performance and reliability of the stacked structure.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132127361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Improved impact-ionization modelling and validation with pn-junction diodes 改进的冲击电离建模和验证与pn结二极管

2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604503

Zhihao Pan, S. Holland, D. Schroeder, W. Krautschneider

{"title":"Improved impact-ionization modelling and validation with pn-junction diodes","authors":"Zhihao Pan, S. Holland, D. Schroeder, W. Krautschneider","doi":"10.1109/SISPAD.2010.5604503","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604503","url":null,"abstract":"Impact-ionization at low and high electric field as well as the temperature dependence has to be modeled well in order to improve the predictive capability of TCAD tools. The high field behavior is of particular interest for ESD protection devices with low breakdown voltages which are used to protect ICs made with modern technologies. In this paper, the model for estimating the impact-ionization proposed by Valdinoci [1] with the parameters of Reggiani [2] has been examined with diodes of various breakdown voltages. It was found that the experimental breakdown voltages of the diodes are underestimated using that model. The cause was traced back to the overestimation of the electron impact-ionization coefficient at high electric fields. By adjusting the model parameters to the experiments of Van Overstraeten [3] and Grant [4], who measured the impact-ionization coefficient in silicon for fields up to 7.7 × 105 V/cm, we extend the model's validity to high fields. With the new parameter set, a much better agreement to the measured breakdown voltages is obtained. As a check for the temperature dependence of the impact-ionization, the diodes were further investigated under 100 ns transmission line pulses (TLP). The measured high-current I–V characteristic is well reproduced by simulations using the new model, as opposed to the well-established model based on Chynoweth's law. Both the failure level and the damage location are well predicted by the simulation.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"282 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114167755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Dissipative transport in Multigate silicon nanowire transistors 多栅极硅纳米线晶体管的耗散输运

2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604559

N. Dehdashti, A. Kranti, I. Ferain, Chi-Woo Lee, R. Yan, P. Razavi, R. Yu, J. Colinge

引用次数: 5

Fabry-Perot oscillations in the thermopower of ballistic graphene ribbons 弹道石墨烯带热能中的法布里-珀罗振荡

2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604579

G. Kliros, P. Divari

引用次数: 1

Stochastic modeling hysteresis and resistive switching in bipolar oxide-based memory 双极氧化物存储器中的随机建模、迟滞和电阻开关

2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604517

A. Makarov, V. Sverdlov, S. Selberherr

引用次数: 4

Simulation of line-edge roughness effects in silicon nanowire MOSFETs 硅纳米线mosfet中线边缘粗糙度效应的模拟

2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604534

Tao Yu, Runsheng Wang, Ru Huang

引用次数: 4

Microscopic simulation of electron transport and self-heating effects in InAs Nanowire MISFETs 纳米线misfet中电子输运和自热效应的微观模拟

2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604558

T. Sadi, J. Thobel, F. Dessenne

引用次数: 2

TCAD simulation vs. experimental results in FDSOI technology: From advanced mobility modeling to 6T-SRAM cell characteristics prediction FDSOI技术中的TCAD仿真与实验结果:从先进的移动性建模到6T-SRAM单元特性预测

2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604506

M. Jaud, P. Scheiblin, S. Martinie, M. Cassé, O. Rozeau, J. Dura, J. Mazurier, A. Toffoli, O. Thomas, F. Andrieu, O. Weber

引用次数: 6

Si nanowire device and its modeling 硅纳米线器件及其建模

2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604569

H. Iwai, K. Natori, K. Kakushima, P. Ahmet, A. Oshiyama, K. Shiraishi, J. Iwata, K. Yamada, K. Ohmori

{"title":"Si nanowire device and its modeling","authors":"H. Iwai, K. Natori, K. Kakushima, P. Ahmet, A. Oshiyama, K. Shiraishi, J. Iwata, K. Yamada, K. Ohmori","doi":"10.1109/SISPAD.2010.5604569","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604569","url":null,"abstract":"Because of its nature of effectively suppressing the off-leakage current with gate around configuration, the Si nanowire FET has been thought be the ultimate structure for for ultra-small CMOS devices towards their downsizing limit. Recently, several experimental data of Si nanowire FETs with very high on-current much larger than that of planar MOSFETs have been published. Thus, Si nanowire FETs are now drawing attention as the most promising candidate for the mainstream CMOS devices in 2020s. In order for the Si nanowire FETs to be introduced into integrated circuits, good compact models which circuit designers can easily handle with are essential. However, it is a really challenging task to establish the compact model, because Id-Vd characteristics of the Si nanowire FETs are affected by the band structure of the nanowire, and the band structure are very sensitive with the nanowire diameter, cross-sectional shape, crystal orientation, mechanical stress, and interface states. In this paper, recent research status of Si nanowire FETs in experimental and theoretical works are described.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115446529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Giant piezoresistance effect in p-type silicon p型硅的巨压阻效应

2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604493

T. T. T. Nghiêm, V. Aubry-Fortuna, C. Chassat, A. Bosseboeuf, P. Dollfus

引用次数: 0