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2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)最新文献

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Logic testing with test-per-clock pattern loading and improved diagnostic abilities 使用每时钟测试模式加载的逻辑测试和改进的诊断能力
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-01 DOI: 10.1109/DDECS.2017.7934586
O. Novák, Z. Plíva
{"title":"Logic testing with test-per-clock pattern loading and improved diagnostic abilities","authors":"O. Novák, Z. Plíva","doi":"10.1109/DDECS.2017.7934586","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934586","url":null,"abstract":"This paper describes a test response compaction system that preserves diagnostic information and enables performing a test-per-clock offline testing. The test response compaction system is based on a chain of T flip-flops. The T flip-flop signature chain can preserve the information about the position of the first occurrence of the erroneous test response and the information about the clock cycle when the erroneous test response occurred. This information can be used for diagnostic purposes. The paper discusses the possible benefits and limitations of the proposed test pattern compaction scheme. The influence of multiple errors on detection and localization capability of the compaction system and hardware overhead is discussed in the paper as well.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128463867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A novel architecture for LZSS compression of configuration bitstreams within FPGA 一种FPGA内LZSS配置位流压缩的新架构
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-01 DOI: 10.1109/DDECS.2017.7934587
R. Iša, J. Matoušek
{"title":"A novel architecture for LZSS compression of configuration bitstreams within FPGA","authors":"R. Iša, J. Matoušek","doi":"10.1109/DDECS.2017.7934587","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934587","url":null,"abstract":"Partial run-time reconfigurability of current FPGAs has been shown to be beneficial in many application domains. However, utilization of this feature is limited by the time it takes to reconfigure a selected part of an FPGA. This is commonly addressed by compression of a configuration bitstream, often using LZSS algorithm. To allow speeding up the reconfiguration also in self-adaptive architectures, bitstream compression has to be done within FPGA. Therefore, this paper presents a novel architecture of an LZSS compression engine that is able to achieve very low resource utilization or throughput several times higher than similar architectures, while keeping the other parameter as well as compression ratio at acceptable level. The presented architecture is generic, thus the user can tune the input token size and the size of buffers to achieve desired characteristics. The paper also includes an evaluation of a trade-off among the size of input token, the size of buffers utilized in LZSS algorithm, and a compression ratio for several configuration bitstreams. This evaluation can help the user to select the right set of parameters for the architecture.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130935202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Relaxed equivalence checking: a new challenge in logic synthesis 松弛等价检验:逻辑综合中的新挑战
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-01 DOI: 10.1109/DDECS.2017.7968435
Z. Vašíček
{"title":"Relaxed equivalence checking: a new challenge in logic synthesis","authors":"Z. Vašíček","doi":"10.1109/DDECS.2017.7968435","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7968435","url":null,"abstract":"The functional equivalence has always been the integral part of virtually every logic synthesis tool. The formal equivalence checking represents a key process that helps logic synthesis tool guarantee that two representations of a circuit designexhibitexactlythesamebehavior.Amongothers,equivalence checking is routinely applied to prove that a synthesized digital circuit is logically equivalent to the RTL source code. Although formal equivalence checking has matured greatly during the last two decades and designs with millions of gates can be handled and verified in reasonable time, a new challenge has emerged with the recent advent of approaches addressing the problem of synthesis of approximate circuits.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127087224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Fault detection and self repair in Hsiao-code FEC circuits 小码FEC电路的故障检测与自修复
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-01 DOI: 10.1109/DDECS.2017.7934588
D. Dicorato, P. Pfeifer, H. Vierhaus
{"title":"Fault detection and self repair in Hsiao-code FEC circuits","authors":"D. Dicorato, P. Pfeifer, H. Vierhaus","doi":"10.1109/DDECS.2017.7934588","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934588","url":null,"abstract":"Wireless signal transmission has become the essential core of modern communication systems. Forward error correction (FEC) has a critical role in securing quality and reliability. FEC circuitry, implemented in nano-technologies, may suffer from transient and permanent fault effects such as radiation-induced single event upsets (SEUs) and aging effects. Such circuits may actually mask non-permanent hardware faults, but possibly at the expense of transmission error correction. Single error correction (SEC)-double error detection (DED) methods are favorably used for rapid error correction within a single clock cycle, and they may even be used for multiple error correction in iterative approaches. But such schemes fail in case hardware faults and transmission faults combine. Where FEC circuits are used in systems that need to be highly dependable over a long life time or which may have limited access for repair, the option of built-in self repair (BISR) may become a must.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115729875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Mealy-to-moore transformation Mealy-to-moore转换
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-01 DOI: 10.1109/DDECS.2017.7934561
Mustafa Ozgul, F. Deeg, S. Sattler
{"title":"Mealy-to-moore transformation","authors":"Mustafa Ozgul, F. Deeg, S. Sattler","doi":"10.1109/DDECS.2017.7934561","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934561","url":null,"abstract":"In this paper we will show a method for transforming an asynchronously feed-backed Mealy machine into an equivalent Moore machine under use of dual-rail logic and the RS-Buffer. The resulting machine will be safe, stable and reproducable. We will further present a use-case to demonstrate the before mentioned transformation.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124974644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Are XORs in logic synthesis really necessary? xor在逻辑合成中真的有必要吗?
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-01 DOI: 10.1109/DDECS.2017.7934583
Ivo Halecek, P. Fiser, Jan Schmidt
{"title":"Are XORs in logic synthesis really necessary?","authors":"Ivo Halecek, P. Fiser, Jan Schmidt","doi":"10.1109/DDECS.2017.7934583","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934583","url":null,"abstract":"This paper follows recent research on insufficient synthesis performance for XOR-intensive circuits, and introduces a novel logic representation with a native support of XOR gates, the XOR-AND-Inverter Graphs (XAIGs). A rewriting algorithm over XAIG has been implemented in the logic synthesis and optimization package ABC, as the first step towards a complete synthesis process. The results show that XAIG based rewriting can help to discover XORs and improves the area of a mapped network in some cases.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130634109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test fast设计:在快于速度测试期间支持x容忍压实
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-01 DOI: 10.1109/DDECS.2017.7934564
M. Kampmann, S. Hellebrand
{"title":"Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test","authors":"M. Kampmann, S. Hellebrand","doi":"10.1109/DDECS.2017.7934564","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934564","url":null,"abstract":"Small Delay Faults (SDFs) on short paths may escape even state-of-the-art at-speed tests. Faster-than-at-Speed Test (FAST) works with increased clock frequencies to detect these faults. However, FAST also introduces an increased amount of unknown logic values (X-values) into the test responses, which makes test response compaction difficult. The paper at hand presents and evaluates a Design for Test (DFT) approach specifically tuned to FAST. It utilizes a special scan-chain configuration in combination with an adaptive masking scheme - the required mask data is generated by respective frequency-aware algorithms. Experimental results indicate that this combination of scan-chain configuration and output masking can achieve high reduction in X-values (up to 95%) without too much loss of fault information at a reasonable amount of control overhead. The approach also has a significant impact on the number of intermediate signatures required by an X-canceling MISR, which can be reduced by up to 68%.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122204791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Implementation of an asynchronous bundled-data router for a GALS NoC in the context of a VSoC 在VSoC环境中，GALS NoC的异步绑定数据路由器的实现
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-01 DOI: 10.1109/DDECS.2017.7934579
P. Russell, Jens Döge, Christoph Hoppe, Thomas B. Preußer, Peter Reichel, P. Schneider
{"title":"Implementation of an asynchronous bundled-data router for a GALS NoC in the context of a VSoC","authors":"P. Russell, Jens Döge, Christoph Hoppe, Thomas B. Preußer, Peter Reichel, P. Schneider","doi":"10.1109/DDECS.2017.7934579","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934579","url":null,"abstract":"Designs of asynchronous networks-on-chip are of growing interest because a complete asynchronous implementation can solve the synchronization problems of large networks. However, asynchronous circuits suffer from the lack of proper design flows because their functionality often relies on timing constraints, which are not extensively supported by common CAD synthesis tools. This paper proposes the design and implementation of an asynchronous router architecture suitable for a network-on-chip in the context of a Vision-System-on-Chip. The developed design flow for the synthesis of asynchronous bundled-data pipelines is based on common synthesis tools and, therefore, enables high compatibility with synchronous designs and a low barrier to entry.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125471993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
On the robustness of memristor based logic gates 基于忆阻器的逻辑门的鲁棒性研究
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-01 DOI: 10.1109/DDECS.2017.7934559
Lei Xie, Hoang Anh Du Nguyen, Jintao Yu, M. Taouil, S. Hamdioui
{"title":"On the robustness of memristor based logic gates","authors":"Lei Xie, Hoang Anh Du Nguyen, Jintao Yu, M. Taouil, S. Hamdioui","doi":"10.1109/DDECS.2017.7934559","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934559","url":null,"abstract":"As today's CMOS technology is scaling down to its physical limits, it suffers from major challenges such as increased leakage power and reduced reliability. Novel technologies, such as memristors, nanotube, and graphene transistors, are under research as alternatives. Among these technologies, memristor is a promising candidate due to its great scalability, high integration density and near-zero standby power. However, memristor-based logic circuits are facing robustness challenges mainly due to improper values of design parameters (e.g., OFF/ON ratio, control voltages). Moreover, process variation, sneak path currents and parasitic resistance of nanowires also impact the robustness. To realize a robust design, this paper formulates proper constraints for design parameters to guarantee correct functionality of logic gates (e.g., AND). Our proposal is verified with SPICE simulations while taking both device variation and parasitic effects into account. It is observed that the errors due to analytical parameter constraints are typically within 4.5% as compared to simulations.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"67 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131950818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Firmware Update Manager: A remote firmware reprogramming tool for low-power devices 固件更新管理器:用于低功耗设备的远程固件重编程工具
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-01 DOI: 10.1109/DDECS.2017.7934581
Ondrej Kachman, M. Baláz
{"title":"Firmware Update Manager: A remote firmware reprogramming tool for low-power devices","authors":"Ondrej Kachman, M. Baláz","doi":"10.1109/DDECS.2017.7934581","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934581","url":null,"abstract":"Modern intelligent systems often consist of devices based on various platforms. When the reprogramming of some devices is required, every type of a device has its own reprogramming mechanism. These mechanisms are usually platform specific, as they are based on a compiler and linker used. This paper presents a GUI based software tool for an easy generation and management of firmware updates for low-power embedded devices. It supports any platform that uses object files with the standard executable and linkable format (ELF). The paper also describes algorithms and methods embedded within the tool. The main contribution of our tool is its configurability and multiplatform support.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114844277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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