{"title":"Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test","authors":"M. Kampmann, S. Hellebrand","doi":"10.1109/DDECS.2017.7934564","DOIUrl":null,"url":null,"abstract":"Small Delay Faults (SDFs) on short paths may escape even state-of-the-art at-speed tests. Faster-than-at-Speed Test (FAST) works with increased clock frequencies to detect these faults. However, FAST also introduces an increased amount of unknown logic values (X-values) into the test responses, which makes test response compaction difficult. The paper at hand presents and evaluates a Design for Test (DFT) approach specifically tuned to FAST. It utilizes a special scan-chain configuration in combination with an adaptive masking scheme - the required mask data is generated by respective frequency-aware algorithms. Experimental results indicate that this combination of scan-chain configuration and output masking can achieve high reduction in X-values (up to 95%) without too much loss of fault information at a reasonable amount of control overhead. The approach also has a significant impact on the number of intermediate signatures required by an X-canceling MISR, which can be reduced by up to 68%.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DDECS.2017.7934564","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
Small Delay Faults (SDFs) on short paths may escape even state-of-the-art at-speed tests. Faster-than-at-Speed Test (FAST) works with increased clock frequencies to detect these faults. However, FAST also introduces an increased amount of unknown logic values (X-values) into the test responses, which makes test response compaction difficult. The paper at hand presents and evaluates a Design for Test (DFT) approach specifically tuned to FAST. It utilizes a special scan-chain configuration in combination with an adaptive masking scheme - the required mask data is generated by respective frequency-aware algorithms. Experimental results indicate that this combination of scan-chain configuration and output masking can achieve high reduction in X-values (up to 95%) without too much loss of fault information at a reasonable amount of control overhead. The approach also has a significant impact on the number of intermediate signatures required by an X-canceling MISR, which can be reduced by up to 68%.