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2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)最新文献

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HLS design of a hardware accelerator for Homomorphic Encryption 同态加密硬件加速器的HLS设计
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-19 DOI: 10.1109/DDECS.2017.7934578
A. Mkhinini, P. Maistri, R. Leveugle, R. Tourki
{"title":"HLS design of a hardware accelerator for Homomorphic Encryption","authors":"A. Mkhinini, P. Maistri, R. Leveugle, R. Tourki","doi":"10.1109/DDECS.2017.7934578","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934578","url":null,"abstract":"Modular polynomial multiplication is the most computationally intensive operation in many homomorphic encryption schemes. In order to accelerate homomorphic computations, we propose a software/hardware (SW/HW) co-designed accelerator integrating fast software algorithms with a configurable hardware polynomial multiplier. The hardware accelerator is implemented through a High-Level Synthesis (HLS) flow. We show that our approach is highly flexible, since the same generic high-level description can be configured and re-used to generate a new design with different parameters and very large sizes in negligible time. We show that flexibility does not preclude efficiency: the proposed solution is competitive in comparison with hand-made designs and can provide good performance at low cost.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131290807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Structure-preserving modeling of safety-critical combinational circuits 安全关键组合电路的保结构建模
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-19 DOI: 10.1109/DDECS.2017.7934554
Feim Ridvan Rasim, Canan Kocar, S. Sattler
{"title":"Structure-preserving modeling of safety-critical combinational circuits","authors":"Feim Ridvan Rasim, Canan Kocar, S. Sattler","doi":"10.1109/DDECS.2017.7934554","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934554","url":null,"abstract":"In this work, a representative combinational circuit is abstracted from transistor level to gate level and a structure preserving transition is carried out into a signal flow graph.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"2 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120981870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A scalable technique to identify true critical paths in sequential circuits 一种在顺序电路中识别真正关键路径的可扩展技术
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-19 DOI: 10.1109/DDECS.2017.7934568
R. Ubar, S. Kostin, M. Jenihhin, J. Raik
{"title":"A scalable technique to identify true critical paths in sequential circuits","authors":"R. Ubar, S. Kostin, M. Jenihhin, J. Raik","doi":"10.1109/DDECS.2017.7934568","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934568","url":null,"abstract":"The recent advancements in the implementation technologies have brought to the front a wide spectrum of new defect types and reliability phenomena. The conventional design techniques do not cope with the integration capacity and stringent requirements of today's nanometer technology nodes. Timing-critical paths analysis is one of such tasks. It has applications in gate-level reliability analysis, e.g., Bias Temperature Instability (BTI) induced aging, but also several others. In this paper, we propose a scalable simulation based technique for explicit identification of true timing-critical paths in both combinational and sequential circuits to enable reliability mitigation approaches, like deciding the paths for delay monitor insertion, resizing delay critical gates or applying rejuvenation stimuli. The paper demonstrates an efficient application of the proposed technique to gate-level NBTI-critical paths identification. The experimental results prove feasibility and scalability of the technique.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132764273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Measuring metastability using a time-to-digital converter 使用时间-数字转换器测量亚稳态
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-19 DOI: 10.1109/DDECS.2017.7934582
T. Polzer, F. Huemer, A. Steininger
{"title":"Measuring metastability using a time-to-digital converter","authors":"T. Polzer, F. Huemer, A. Steininger","doi":"10.1109/DDECS.2017.7934582","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934582","url":null,"abstract":"In view of the numerous clock domain crossings found in modern systems-on-chip and multicore architectures precise metastability characterization is a fundamental task. We propose a conceptually novel approach for the experimental assessment of upset rate over resolution time that is usually employed to extract the relevant characteristics. Our method is based on connecting a time-to-digital converter to the output of the flip flop under test, rather than using a phase shifted clock, as conventionally done. We present the details of an FPGA implementation of our approach and show its feasibility through an experimental evaluation, whose results favorably match those obtained by the conventional method. The benefits of the novel scheme are the ability to perform a calibration for the delay steps, a speed-up of the measurement process, and the availability of a more comprehensive and ordered measurement data set.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133989217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Formal Design Space Exploration for memristor-based crossbar architecture 基于忆阻器的横杆建筑形式设计空间探索
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-19 DOI: 10.1109/DDECS.2017.7934557
Marcello Traiola, M. Barbareschi, A. Bosio
{"title":"Formal Design Space Exploration for memristor-based crossbar architecture","authors":"Marcello Traiola, M. Barbareschi, A. Bosio","doi":"10.1109/DDECS.2017.7934557","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934557","url":null,"abstract":"The unceasing shrinking process of CMOS technology is leading to its physical limits, impacting several aspects, such as performances, power consumption and many others. Alternative solutions are under investigation in order to overcome CMOS limitations. Among them, the memristor is one of promising technologies. Several works have been proposed so far, describing how to synthesize boolean logic functions on memristors-based crossbar architecture. However, depending on the synthesis parameters, different architectures can be obtained. Design Space Exploration (DSE) is therefore mandatory to help and guide the designer in order to select the best crossbar configuration. In this paper, we present a formal DSE approach. The main advantage is that it does not require any simulation and thus it avoids any runtime overheads. Preliminary results show the huge gain in runtime compared to simulation-based DSE.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130090674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
From online fault detection to fault management in Network-on-Chips: A ground-up approach 从在线故障检测到片上网络的故障管理:一种自下而上的方法
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-19 DOI: 10.1109/DDECS.2017.7934565
Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, N. George, S. Oyeniran, Tsotne Putkaradze, Apneet Kaur, J. Raik, G. Jervan, R. Ubar, T. Hollstein
{"title":"From online fault detection to fault management in Network-on-Chips: A ground-up approach","authors":"Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, N. George, S. Oyeniran, Tsotne Putkaradze, Apneet Kaur, J. Raik, G. Jervan, R. Ubar, T. Hollstein","doi":"10.1109/DDECS.2017.7934565","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934565","url":null,"abstract":"Due to the ongoing miniaturization of silicon technology beyond the sub-micron domain and the trend of integrating ever more components on a single chip, the Network-on-Chip (NoC) paradigm has emerged to address the scalability and performance shortcomings of bus-based interconnects. As the feature size shrinks, the system gets much more susceptible to faults caused by wear-out and environmental effects. Thus, in order to increase the reliability, creates the need for having mechanisms embedded into such a system that could detect and manage the faults in run-time. In this paper, a ground-up approach from fault detection to fault management for such a NoC-based system on chip is proposed that utilizes both local fault management for fast reaction to faults and a global fault management mechanisms for triggering a large-scale reconfiguration of the NoC. Also, detailed description of strategies for fault detection, localization, classification and propagation to a global fault management unit are provided and methods for local fault management are elaborated.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"352 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115977837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Routing approach for digital, differential bipolar designs using virtual fat-wire boundary pins 采用虚拟胖线边界引脚的数字差分双极设计的布线方法
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-19 DOI: 10.1109/DDECS.2017.7934555
O. Schrape, Manuel Herrmann, F. Winkler, M. Krstic
{"title":"Routing approach for digital, differential bipolar designs using virtual fat-wire boundary pins","authors":"O. Schrape, Manuel Herrmann, F. Winkler, M. Krstic","doi":"10.1109/DDECS.2017.7934555","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934555","url":null,"abstract":"This paper presents an alternative fat-wire routing approach for differential bipolar high-speed designs. The proposed solution obtains parallel routing and well balanced capacitive load of the fully differential signaling. In contrast to other approaches, the proposed flow is optimized for complex bipolar CML/ECL standard cell designs and technology options with few available routing layers. It enables the use of advanced placement and routing methods, such as multi-oriented cell placement and in-place optimization, supported by the standard CAD tools. The standard cell requirements and the corresponding modified digital design flow are proposed and discussed. The presented strategy is evaluated on a 12.5 GHz PLL feedback clock divider which has been fully implemented with differential ECL standard cell gates. A discussion regarding the obtained results finalizes this paper.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131285592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Ultra-low-voltage driver for large load capacitance in 130nm CMOS technology 超低电压驱动器，适用于130nm CMOS技术的大负载电容
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-19 DOI: 10.1109/DDECS.2017.7934567
Michal Sovcík, M. Kovác, D. Arbet, V. Stopjaková
{"title":"Ultra-low-voltage driver for large load capacitance in 130nm CMOS technology","authors":"Michal Sovcík, M. Kovác, D. Arbet, V. Stopjaková","doi":"10.1109/DDECS.2017.7934567","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934567","url":null,"abstract":"This paper presents design of the inverter-based driver for low-voltage applications, with topology for boosting the transistors overdrive voltage. The proposed driver topology was designed through detailed circuit analysis and optimization, and it is suitable for use in a switched capacitor charge pump. The driver was designed in 130 nm CMOS technology and verified by simulations including technology corners. Core of the proposed driver — the inverter uses power supply voltage of 200 mV. The whole boosted driver achieves a propagation delay of 9.2 ns and energy consumption of 92.12 µW for the value of load capacitor is 100 pF. Due to the low-power consumption, the proposed driver was satisfactory used in a self-powered charge pump systems.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132036528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Analog front-end for precise human body temperature measurement 模拟前端精确人体体温测量
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-19 DOI: 10.1109/DDECS.2017.7934570
Paweł Narczyk, Krzysztof Siwiec, W. Pleskacz
{"title":"Analog front-end for precise human body temperature measurement","authors":"Paweł Narczyk, Krzysztof Siwiec, W. Pleskacz","doi":"10.1109/DDECS.2017.7934570","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934570","url":null,"abstract":"Analog front-end for precise temperature measurement of a human body has been presented. The discussed analog front-end (AFE) contains a new temperature calibration technique based on on-chip resistor. The described calibration method allows to obtain very high accuracy, even 0.1 °C, in very wide range of an operating temperature of an integrated circuit. The AFE consists of a bandgap current reference, a precision current source, a programmable gain amplifier, a voltage source proportional to absolute temperature and on-chip temperature calibration resistor. The presented analog front-end consumes no more than 180 uW and was designed and manufactured in UMC CMOS 130 nm technology. All data presented in the article were obtained from measurements. Measurements were taken using manual wafer prober with climate control microchamber, at temperature range from −40 °C to 125 °C.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115548639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Hierarchical temporal memory implementation on FPGA using LFSR based spatial pooler address space generator 基于LFSR的空间池地址空间生成器在FPGA上实现分层时间存储器
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-19 DOI: 10.1109/DDECS.2017.7934577
Madis Kerner, K. Tammemäe
{"title":"Hierarchical temporal memory implementation on FPGA using LFSR based spatial pooler address space generator","authors":"Madis Kerner, K. Tammemäe","doi":"10.1109/DDECS.2017.7934577","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934577","url":null,"abstract":"Hierarchical temporal memory (HTM) is the model of the neocortex functionality, developed by Numenta, Inc. The level of implementation does cover only the subset of actual neocortex layers functionality, but, however, is sufficient to be useful in different domain areas e.g. for a novelty or anomaly detection. Numenta provides their implementation of the HTM for commercial or research purposes as a software solution. The purpose of this work is to investigate the feasibility of implementing the HTM algorithm partly or entirely on FPGA, providing the suitable building block for the resource limited cyber physical systems. The uniqueness of the provided solution is based on resource efficient Linear Feedback Shift Registers (LFSR) as connection address generators, as well as using a simple serial interface for inter-column communication.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125036319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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