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2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)最新文献

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Novel metrics for Analog Mixed-Signal coverage 模拟混合信号覆盖的新指标
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-01 DOI: 10.1109/DDECS.2017.7934589
Andreas Furtig, G. Glaeser, C. Grimm, L. Hedrich, S. Heinen, Hyun-Sek Lukas Lee, Gregor Nitsche, M. Olbrich, Carna Radojicic, Fabian Speicher
{"title":"Novel metrics for Analog Mixed-Signal coverage","authors":"Andreas Furtig, G. Glaeser, C. Grimm, L. Hedrich, S. Heinen, Hyun-Sek Lukas Lee, Gregor Nitsche, M. Olbrich, Carna Radojicic, Fabian Speicher","doi":"10.1109/DDECS.2017.7934589","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934589","url":null,"abstract":"On the contrary to the digital world, no coverage definition exists in the Analog/Mixed-Signal (AMS) context. As digital coverage helps digital designers and verification engineers to evaluate their verification progress, analog designers do not have such metrics. This paper proposes a set of different analog coverage metrics, which improve the confidence in AMS circuit verification. We will demonstrate, that no single overall coverage metric exists. However, as with digital coverage, the proposed analog coverage metrics could substantially help in rating the verification process. Illustrated by a complex AMS circuit example we will explore the limits of analog coverage methodologies as well as the benefits on different levels of abstraction ranging from transistor level up to system level.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122264363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A low power input amplifier for bio-signal acquisition in 28 nm FDSOI technology 用于28纳米FDSOI技术的生物信号采集的低功率输入放大器
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-01 DOI: 10.1109/DDECS.2017.7934562
M. Wolodzko, W. Kuzmicz
{"title":"A low power input amplifier for bio-signal acquisition in 28 nm FDSOI technology","authors":"M. Wolodzko, W. Kuzmicz","doi":"10.1109/DDECS.2017.7934562","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934562","url":null,"abstract":"In this paper a low power amplifier for bio-signal acquisition is described. The design takes benefit of UTBB-FDSOI 28nm technology and exploits bulk under the buried oxide as a second gate of FET device. This amplifier exhibits low supply current of 25nA, while keeping input noise at 24 µV in bio-signal frequency band. The gain of the amplifier is 71dB.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123423563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design for three-dimensional sound processor using high-level synthesis 采用高级合成技术设计三维声音处理器
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-01 DOI: 10.1109/DDECS.2017.7934556
S. Ohira, T. Matsumura
{"title":"Design for three-dimensional sound processor using high-level synthesis","authors":"S. Ohira, T. Matsumura","doi":"10.1109/DDECS.2017.7934556","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934556","url":null,"abstract":"We propose a three-dimensional (3D) sound processor architecture that includes super-directional modulation intellectual property (IP) and 3D sound processing IP for consumer applications. This processor can generate realistic small sound fields in arbitrary spaces by using ultrasound. The architecture is designed with high-level synthesis as the design methodology. By inputting a description of several design parameters, such as the number of IPs and the order and coefficients of the filters on SystemC, the processer hardware can be synthesized automatically. The total amount of hardware used for the super-directional modulation IP and the 3D sound processing IP is 6,021 Nets and 1,292 LCs. The 3D sound processor was implemented on a Xilinx FPGA to verify its function and performance.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133279521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Improving combinational circuit resilience against soft errors via selective resource allocation 通过选择性资源分配提高组合电路对软错误的弹性
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-01 DOI: 10.1109/DDECS.2017.7934576
Tohid Taghizad Gogjeh Yaran, S. Tosun
{"title":"Improving combinational circuit resilience against soft errors via selective resource allocation","authors":"Tohid Taghizad Gogjeh Yaran, S. Tosun","doi":"10.1109/DDECS.2017.7934576","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934576","url":null,"abstract":"Combinational circuits have become more vulnerable to soft errors (SEs) in each CMOS technology generation. Most of the prior studies use hardware redundancy in an attempt to harden the circuits against errors. However, redundancy increases the area and power consumption. Furthermore, the design constraints may not allow adding redundant resources to the final circuit. In this paper, we present a genetic algorithm (GA)-based design method to increase the reliability of combinational circuits. In this method, we use different versions of the same resources, each having different area, latency, and reliability values. The goal of GA-based method is to allocate the best available resources to the application nodes to maximize the reliability of the design under tight area and latency constraints. Our experimental results show that we achieve up to 19.90% (14.50% on average) reliability improvement against a heuristic method with no additional area overhead.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132428743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
PMS2UPF: An automated transition from ESL to RTL power-intent specification PMS2UPF:从ESL到RTL功率意图规范的自动转换
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-01 DOI: 10.1109/DDECS.2017.7934558
Miroslav Siro, Dominik Macko, K. Jelemenská
{"title":"PMS2UPF: An automated transition from ESL to RTL power-intent specification","authors":"Miroslav Siro, Dominik Macko, K. Jelemenská","doi":"10.1109/DDECS.2017.7934558","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934558","url":null,"abstract":"High power density is the most crucial problem in deeply integrated hardware systems. Therefore, the power has to be reduced in such systems, what is most commonly achieved by the utilization of power management. Unfortunately, the standardized application of power management is quite complex and does not very well support the system level of design abstraction, which is increasingly used by the industry. An immediately applicable solution to this problem is to use increased automation in the design process, regarding the power management. This paper proposes a tool, called PMS2UPF, which can automatically generate the standard UPF (Unified Power Format) power intent based on the abstract power-management specification in SystemC/PMS. The automated transition between the two abstraction levels not only accelerates the design process, but also prevents possible introduction of human errors into the refined design.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121288395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A fast and flexible HW/SW co-processing framework for Time-of-Flight 3D imaging 一种快速灵活的飞行时间3D成像软硬件协同处理框架
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-01 DOI: 10.1109/DDECS.2017.7934585
N. Druml, Christoph Ehrenhofer, Walter Bell, Christian Gailer, H. Plank, T. Herndl, G. Holweg
{"title":"A fast and flexible HW/SW co-processing framework for Time-of-Flight 3D imaging","authors":"N. Druml, Christoph Ehrenhofer, Walter Bell, Christian Gailer, H. Plank, T. Herndl, G. Holweg","doi":"10.1109/DDECS.2017.7934585","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934585","url":null,"abstract":"Time-of-Flight 3D imaging, using the indirect measuring method that employs photonic mixing devices, increases in popularity. This is due to the recent availability of accurate and miniaturized Time-of-Flight cameras that can be integrated into small embedded devices. However, providing a system comprising a camera and hardware-accelerated processing, which is useable for various application types with diametrically opposed use-case requirements, is not trivial.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123727653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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