{"title":"采用高级合成技术设计三维声音处理器","authors":"S. Ohira, T. Matsumura","doi":"10.1109/DDECS.2017.7934556","DOIUrl":null,"url":null,"abstract":"We propose a three-dimensional (3D) sound processor architecture that includes super-directional modulation intellectual property (IP) and 3D sound processing IP for consumer applications. This processor can generate realistic small sound fields in arbitrary spaces by using ultrasound. The architecture is designed with high-level synthesis as the design methodology. By inputting a description of several design parameters, such as the number of IPs and the order and coefficients of the filters on SystemC, the processer hardware can be synthesized automatically. The total amount of hardware used for the super-directional modulation IP and the 3D sound processing IP is 6,021 Nets and 1,292 LCs. The 3D sound processor was implemented on a Xilinx FPGA to verify its function and performance.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Design for three-dimensional sound processor using high-level synthesis\",\"authors\":\"S. Ohira, T. Matsumura\",\"doi\":\"10.1109/DDECS.2017.7934556\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We propose a three-dimensional (3D) sound processor architecture that includes super-directional modulation intellectual property (IP) and 3D sound processing IP for consumer applications. This processor can generate realistic small sound fields in arbitrary spaces by using ultrasound. The architecture is designed with high-level synthesis as the design methodology. By inputting a description of several design parameters, such as the number of IPs and the order and coefficients of the filters on SystemC, the processer hardware can be synthesized automatically. The total amount of hardware used for the super-directional modulation IP and the 3D sound processing IP is 6,021 Nets and 1,292 LCs. The 3D sound processor was implemented on a Xilinx FPGA to verify its function and performance.\",\"PeriodicalId\":330743,\"journal\":{\"name\":\"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DDECS.2017.7934556\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DDECS.2017.7934556","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design for three-dimensional sound processor using high-level synthesis
We propose a three-dimensional (3D) sound processor architecture that includes super-directional modulation intellectual property (IP) and 3D sound processing IP for consumer applications. This processor can generate realistic small sound fields in arbitrary spaces by using ultrasound. The architecture is designed with high-level synthesis as the design methodology. By inputting a description of several design parameters, such as the number of IPs and the order and coefficients of the filters on SystemC, the processer hardware can be synthesized automatically. The total amount of hardware used for the super-directional modulation IP and the 3D sound processing IP is 6,021 Nets and 1,292 LCs. The 3D sound processor was implemented on a Xilinx FPGA to verify its function and performance.