Design for three-dimensional sound processor using high-level synthesis

S. Ohira, T. Matsumura
{"title":"Design for three-dimensional sound processor using high-level synthesis","authors":"S. Ohira, T. Matsumura","doi":"10.1109/DDECS.2017.7934556","DOIUrl":null,"url":null,"abstract":"We propose a three-dimensional (3D) sound processor architecture that includes super-directional modulation intellectual property (IP) and 3D sound processing IP for consumer applications. This processor can generate realistic small sound fields in arbitrary spaces by using ultrasound. The architecture is designed with high-level synthesis as the design methodology. By inputting a description of several design parameters, such as the number of IPs and the order and coefficients of the filters on SystemC, the processer hardware can be synthesized automatically. The total amount of hardware used for the super-directional modulation IP and the 3D sound processing IP is 6,021 Nets and 1,292 LCs. The 3D sound processor was implemented on a Xilinx FPGA to verify its function and performance.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DDECS.2017.7934556","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

We propose a three-dimensional (3D) sound processor architecture that includes super-directional modulation intellectual property (IP) and 3D sound processing IP for consumer applications. This processor can generate realistic small sound fields in arbitrary spaces by using ultrasound. The architecture is designed with high-level synthesis as the design methodology. By inputting a description of several design parameters, such as the number of IPs and the order and coefficients of the filters on SystemC, the processer hardware can be synthesized automatically. The total amount of hardware used for the super-directional modulation IP and the 3D sound processing IP is 6,021 Nets and 1,292 LCs. The 3D sound processor was implemented on a Xilinx FPGA to verify its function and performance.
采用高级合成技术设计三维声音处理器
我们提出了一种三维(3D)声音处理器架构,其中包括超定向调制知识产权(IP)和用于消费者应用的3D声音处理IP。该处理器可以利用超声波在任意空间产生逼真的小声场。该体系结构采用高级综合作为设计方法进行设计。通过在SystemC上输入多个设计参数的描述,如ip数、滤波器的阶数和系数,可以自动合成处理器硬件。用于超定向调制IP和3D声音处理IP的硬件总数为6,021个net和1,292个lc。在Xilinx FPGA上实现了三维声音处理器,验证了其功能和性能。
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