2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)最新文献_第2页

Towards approximation during test of Integrated Circuits 集成电路测试中逼近问题

2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-19 DOI: 10.1109/DDECS.2017.7934574

I. Wali, Marcello Traiola, A. Virazel, P. Girard, M. Barbareschi, A. Bosio

{"title":"Towards approximation during test of Integrated Circuits","authors":"I. Wali, Marcello Traiola, A. Virazel, P. Girard, M. Barbareschi, A. Bosio","doi":"10.1109/DDECS.2017.7934574","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934574","url":null,"abstract":"In the recent years, Approximate Computing (AC) has emerged as a new paradigm for energy efficient design of Integrated Circuits (ICs). AC is based on the intuitive observation that, while performing exact computation requires a high amount of resources, allowing a selective approximation or an occasional relaxation of the specification can provide significant gains in energy efficiency. This work starts from the consideration that AC-based systems can intrinsically accept the presence of faulty hardware (i.e., hardware that can produce errors). In other words, an AC-based system does not need to be built using defect-free ICs. Under this assumption, we can relax test and reliability constraints of the manufactured ICs. One of the ways to achieve this goal is to test only for a subset of faults instead of targeting all possible faults. In this way, we can reduce the manufacturing cost since we reduce the number test patterns and thus the test time. We call this approach Approximate Test (AT). The main advantage is the fact that we do not need a prior knowledge of the application. Therefore, the proposed approach can be applied to any kind of IC, reducing the test time and increasing the yield. In this work, we aim at validating the proposed AT by comparing it with a functional approach. We present preliminary results on some simple case studies. The main goal is to show that by letting some faults undetected we can save test time without having a huge impact on the application quality.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133362092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Cycle-accurate software modeling for RTL verification of embedded systems 嵌入式系统RTL验证的周期精确软件建模

2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-19 DOI: 10.1109/DDECS.2017.7934571

Michael Schwarz, Carlos Villarraga, D. Stoffel, W. Kunz

引用次数: 2

Rocket Queue: New data sorting architecture for real-time systems Rocket Queue:实时系统的新数据排序架构

2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-19 DOI: 10.1109/DDECS.2017.7934573

L. Kohútka, V. Stopjaková

{"title":"Rocket Queue: New data sorting architecture for real-time systems","authors":"L. Kohútka, V. Stopjaková","doi":"10.1109/DDECS.2017.7934573","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934573","url":null,"abstract":"This paper presents the design of a coprocessor that performs data sorting for min/max queues in real-time systems. The proposed architecture is based on shift registers, systolic arrays and heapsort algorithm. Such an architecture, called Rocket Queue, is able not only to sort items according to their sort values, but it is also possible to remove any item from the structure according to its unique ID, which is important for many various applications. Instructions of the Rocket Queue architecture are performed in two clock cycles regardless of the number of items in the system and regardless the queue capacity. The developed coprocessor is optimized for low chip area costs, which leads to lower energy consumption too. The Rocket Queue architecture has constant time complexity, constant critical path length and it is highly predictable, thus also suitable for real-time applications. The architecture was verified using simplified version of UVM and applying millions of instructions with randomly generated sort values. Achieved synthesis results are presented and discussed. These results are significantly better than the results of systolic arrays. More than 41% of logic resources can be saved using the Rocket Queue architecture.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114485842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Optimization of Pearson correlation coefficient calculation for DPA and comparison of different approaches 优化DPA的Pearson相关系数计算及不同方法的比较

2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-19 DOI: 10.1109/DDECS.2017.7934563

Petr Socha, Vojtech Miskovský, H. Kubátová, M. Novotný

引用次数: 13

Body biasing for analog design: Practical experiences in 22 nm FD-SOI 模拟设计的体偏置:22nm FD-SOI的实践经验

2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-01 DOI: 10.1109/DDECS.2017.7934580

S. Rao, Benjamin Prautsch, A. Shrivastava, T. Reich

引用次数: 2

Mapping abstract and concrete hardware models for design understanding 映射抽象和具体的硬件模型，以便设计理解

2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-01 DOI: 10.1109/DDECS.2017.7934569

Tino Flenker, G. Fey

引用次数: 2

Energy-aware application-specific topology generation for 3D Network-on-Chips 三维片上网络的能量感知应用特定拓扑生成

2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-01 DOI: 10.1109/DDECS.2017.7934575

Arash Barzinmehr, S. Tosun

{"title":"Energy-aware application-specific topology generation for 3D Network-on-Chips","authors":"Arash Barzinmehr, S. Tosun","doi":"10.1109/DDECS.2017.7934575","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934575","url":null,"abstract":"Network-on-Chip (NoC) is a promising approach for supporting heavy communication demand among the parts of modern high-performance nanoscale System-on-Chips (SoCs). Three-dimensional integration (3D) for integrated circuits (ICs) has become popular since it reduces the latency and energy consumption by replacing long global interconnects with short vertical through-silicon-via (TSV) interconnects between stacked dies. Combining NoCs with 3D technology seems a good choice for achieving better performances than 2D. Although there are good synthesis methods for energy- and communication-aware 2D-NoC design, we lack the 3D alternatives. Motivated by the needs, in this paper, we propose an energy-aware application-specific topology generation method for 3D-NoCs. Our method is based on a heuristic optimization algorithm that partitions the application nodes among layers of the NoC architecture with an attempt to minimize the dynamic energy consumption. We tested our 3D method against a 2D alternative through several NoC benchmarks. Simulation results show that our approach brings huge energy and area savings against its 2D counterpart.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"252 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115007064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

An efficient physical design of fully-testable BDD-based circuits 完全可测试的基于bdd电路的高效物理设计

2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-01 DOI: 10.1109/DDECS.2017.7934560

Andreas Rauchenecker, R. Wille

引用次数: 1

An analysis of the operation and SET robustness of a CMOS pulse stretching circuit CMOS脉冲拉伸电路的工作和SET鲁棒性分析

2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-01 DOI: 10.1109/DDECS.2017.7934590

M. Andjelković, M. Krstic, R. Kraemer

{"title":"An analysis of the operation and SET robustness of a CMOS pulse stretching circuit","authors":"M. Andjelković, M. Krstic, R. Kraemer","doi":"10.1109/DDECS.2017.7934590","DOIUrl":"https://doi.org/10.1109/DDECS.2017.7934590","url":null,"abstract":"The cascaded asymmetrically sized inverters can be employed as pulse stretchers, for the measurement of very short single event transient (SET) pulse widths (< 200 ps). This paper analyzes, through the circuit simulations, the effects of various design and operating parameters on the normal operation and SET robustness of a two-inverter pulse stretcher designed in 250 nm bulk CMOS technology. It was shown that the SET hardness of the pulse stretcher can be enhanced by upsizing all transistors in the pulse stretcher without changing the sizing ratio. The SET hardness can also be improved by upsizing the load, but this approach is less effective than the pulse stretcher upsizing. Both upsizing approaches have a negligible impact on the normal operation of the stretcher, i.e. output pulse width. In addition, the operation and SET robustness of the pulse stretcher can be influenced by the operating temperature and supply voltage variations, and these effects should be considered in the design process. Based on the acquired simulation results, a general approach for the design of a radiation hardened CMOS pulse stretcher has been proposed.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"105 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122632238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A 50 GHz SiGe BiCMOS active bandpass filter 50 GHz SiGe BiCMOS有源带通滤波器

2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2017-04-01 DOI: 10.1109/DDECS.2017.7934566

Saurabh Chaturvedi, M. Božanić, S. Sinha

引用次数: 6