Rocket Queue: New data sorting architecture for real-time systems

This paper presents the design of a coprocessor that performs data sorting for min/max queues in real-time systems. The proposed architecture is based on shift registers, systolic arrays and heapsort algorithm. Such an architecture, called Rocket Queue, is able not only to sort items according to their sort values, but it is also possible to remove any item from the structure according to its unique ID, which is important for many various applications. Instructions of the Rocket Queue architecture are performed in two clock cycles regardless of the number of items in the system and regardless the queue capacity. The developed coprocessor is optimized for low chip area costs, which leads to lower energy consumption too. The Rocket Queue architecture has constant time complexity, constant critical path length and it is highly predictable, thus also suitable for real-time applications. The architecture was verified using simplified version of UVM and applying millions of instructions with randomly generated sort values. Achieved synthesis results are presented and discussed. These results are significantly better than the results of systolic arrays. More than 41% of logic resources can be saved using the Rocket Queue architecture.