Mapping abstract and concrete hardware models for design understanding

Abstract

Before a microchip's concrete implementation is available a very abstract model is created, e.g., on Electronic System Level (ESL) or even more abstract. To ensure a better design understanding, we propose an automated mapping from a given abstract model to an unfamiliar concrete implementation at Register Transfer Level (RTL). But how to map a variable from the abstract model to a variable from the concrete model? We address this problem by a simulation based approach. We instrument the abstract model to get traces for each variable in both models and propose four heuristics to evaluate which variable maps to a corresponding variable of the other model. Experiments on an Instruction Set Simulator (ISS) versus RTL processor show mappings which offer an insight into the RTL implementation.