Energy-aware application-specific topology generation for 3D Network-on-Chips

Network-on-Chip (NoC) is a promising approach for supporting heavy communication demand among the parts of modern high-performance nanoscale System-on-Chips (SoCs). Three-dimensional integration (3D) for integrated circuits (ICs) has become popular since it reduces the latency and energy consumption by replacing long global interconnects with short vertical through-silicon-via (TSV) interconnects between stacked dies. Combining NoCs with 3D technology seems a good choice for achieving better performances than 2D. Although there are good synthesis methods for energy- and communication-aware 2D-NoC design, we lack the 3D alternatives. Motivated by the needs, in this paper, we propose an energy-aware application-specific topology generation method for 3D-NoCs. Our method is based on a heuristic optimization algorithm that partitions the application nodes among layers of the NoC architecture with an attempt to minimize the dynamic energy consumption. We tested our 3D method against a 2D alternative through several NoC benchmarks. Simulation results show that our approach brings huge energy and area savings against its 2D counterpart.