A novel architecture for LZSS compression of configuration bitstreams within FPGA

Abstract

Partial run-time reconfigurability of current FPGAs has been shown to be beneficial in many application domains. However, utilization of this feature is limited by the time it takes to reconfigure a selected part of an FPGA. This is commonly addressed by compression of a configuration bitstream, often using LZSS algorithm. To allow speeding up the reconfiguration also in self-adaptive architectures, bitstream compression has to be done within FPGA. Therefore, this paper presents a novel architecture of an LZSS compression engine that is able to achieve very low resource utilization or throughput several times higher than similar architectures, while keeping the other parameter as well as compression ratio at acceptable level. The presented architecture is generic, thus the user can tune the input token size and the size of buffers to achieve desired characteristics. The paper also includes an evaluation of a trade-off among the size of input token, the size of buffers utilized in LZSS algorithm, and a compression ratio for several configuration bitstreams. This evaluation can help the user to select the right set of parameters for the architecture.