{"title":"使用每时钟测试模式加载的逻辑测试和改进的诊断能力","authors":"O. Novák, Z. Plíva","doi":"10.1109/DDECS.2017.7934586","DOIUrl":null,"url":null,"abstract":"This paper describes a test response compaction system that preserves diagnostic information and enables performing a test-per-clock offline testing. The test response compaction system is based on a chain of T flip-flops. The T flip-flop signature chain can preserve the information about the position of the first occurrence of the erroneous test response and the information about the clock cycle when the erroneous test response occurred. This information can be used for diagnostic purposes. The paper discusses the possible benefits and limitations of the proposed test pattern compaction scheme. The influence of multiple errors on detection and localization capability of the compaction system and hardware overhead is discussed in the paper as well.","PeriodicalId":330743,"journal":{"name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Logic testing with test-per-clock pattern loading and improved diagnostic abilities\",\"authors\":\"O. Novák, Z. Plíva\",\"doi\":\"10.1109/DDECS.2017.7934586\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a test response compaction system that preserves diagnostic information and enables performing a test-per-clock offline testing. The test response compaction system is based on a chain of T flip-flops. The T flip-flop signature chain can preserve the information about the position of the first occurrence of the erroneous test response and the information about the clock cycle when the erroneous test response occurred. This information can be used for diagnostic purposes. The paper discusses the possible benefits and limitations of the proposed test pattern compaction scheme. The influence of multiple errors on detection and localization capability of the compaction system and hardware overhead is discussed in the paper as well.\",\"PeriodicalId\":330743,\"journal\":{\"name\":\"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DDECS.2017.7934586\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DDECS.2017.7934586","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Logic testing with test-per-clock pattern loading and improved diagnostic abilities
This paper describes a test response compaction system that preserves diagnostic information and enables performing a test-per-clock offline testing. The test response compaction system is based on a chain of T flip-flops. The T flip-flop signature chain can preserve the information about the position of the first occurrence of the erroneous test response and the information about the clock cycle when the erroneous test response occurred. This information can be used for diagnostic purposes. The paper discusses the possible benefits and limitations of the proposed test pattern compaction scheme. The influence of multiple errors on detection and localization capability of the compaction system and hardware overhead is discussed in the paper as well.