2012 IEEE International Conference on Circuits and Systems (ICCAS)最新文献

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A novel ZCS-SR voltage multiplier based high-voltage DC power supply 一种新型的基于ZCS-SR电压乘法器的高压直流电源
2012 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2012-10-01 DOI: 10.1109/ICCIRCUITSANDSYSTEMS.2012.6408344
S. Lee, S. Iqbal, M. Jamil
{"title":"A novel ZCS-SR voltage multiplier based high-voltage DC power supply","authors":"S. Lee, S. Iqbal, M. Jamil","doi":"10.1109/ICCIRCUITSANDSYSTEMS.2012.6408344","DOIUrl":"https://doi.org/10.1109/ICCIRCUITSANDSYSTEMS.2012.6408344","url":null,"abstract":"This paper presents a novel topology based on the zero current switching series resonant (ZCS-SR) converter for high-voltage application. The proposed topology consists of two series resonant tanks. Each series resonant tank is built up by connecting a tank capacitor in series to a high-voltage transformer with the leakage inductance of the high-voltage transformer is absorbed as resonant inductor. Therefore, two high-voltage transformers are used in this topology with their primary windings are connected in series. The secondary output of both transformers are boosted by half-wave voltage multiplier and mixed before supply to load. The series resonant tanks are energized alternately by controlling two IGBT switches with pulse frequency modulation (PFM). This topology is operating in discontinuous conduction mode (DCM) with all IGBT switches are operating in zero current switching (ZCS) condition and hence no switching loss occurs. Moreover, this topology has low conduction loss as it requires only half number of IGBT switches compared to conventional full-bridge inverter based SRC. The effectiveness of the proposed topology is verified by simulation using OrCAD PSpice and the simulation results will be presented.","PeriodicalId":325846,"journal":{"name":"2012 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129297945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Interpolator algorithms for approximating the LNS addition and subtraction: Design and analysis 近似LNS加减法的插值算法:设计与分析
2012 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2012-10-01 DOI: 10.1109/ICCIRCUITSANDSYSTEMS.2012.6408336
R. C. Ismail, R. Hussin, S. Murad
{"title":"Interpolator algorithms for approximating the LNS addition and subtraction: Design and analysis","authors":"R. C. Ismail, R. Hussin, S. Murad","doi":"10.1109/ICCIRCUITSANDSYSTEMS.2012.6408336","DOIUrl":"https://doi.org/10.1109/ICCIRCUITSANDSYSTEMS.2012.6408336","url":null,"abstract":"The logarithmic number system (LNS) can be considered a good alternative to floating-point, specifically for applications that require a wide range of dynamic numbers for arithmetic operations. To date, its implementation is still restricted by the complexity of performing addition and subtraction operations as a result of using large lookup tables. In previous works, interpolation has been widely used to approximate these non-linear functions. Therefore in this paper, an analysis is presented to identify the most suitable algorithm to be employed for approximating the LNS addition and subtraction functions at 32-bit precisions. The selection is based on the minimum amount of storage that can be attained whilst maintaining its accuracy within the floating-point (FLP) limit. From the results it is clear that there is a potential procedure which can fulfil the above criteria, and that could possibly be applied in the future implementation of an LNS system.","PeriodicalId":325846,"journal":{"name":"2012 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124812728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design perspective of multi-channel data acquisition and logger system for CPV technology 基于CPV技术的多通道数据采集与记录仪系统设计思路
2012 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2012-10-01 DOI: 10.1109/ICCIRCUITSANDSYSTEMS.2012.6408297
Navid Torabpourshiraz, Shankar Duraikannan, Chandrasekharan Nataraj
{"title":"Design perspective of multi-channel data acquisition and logger system for CPV technology","authors":"Navid Torabpourshiraz, Shankar Duraikannan, Chandrasekharan Nataraj","doi":"10.1109/ICCIRCUITSANDSYSTEMS.2012.6408297","DOIUrl":"https://doi.org/10.1109/ICCIRCUITSANDSYSTEMS.2012.6408297","url":null,"abstract":"The world demand for alternative energy source has increased with the consumption of energy increasing tenfold in the past five decades. Solar power generation is one such alternative, and Concentrated Photovoltaic Technology (CPV) is one of the two main technologies used for producing electricity from Concentrated Solar Power (CSP). Meteorological parameters such as solar irradiance and cell temperature when the sunlight is concentrated on the CPV module influence the efficiency of the CPV power generation systems. Additionally, the output power of a CPV plant must be measured and monitored to improve the condition of plant, again in terms of efficiency and reliability. Firstly, in this paper, the significance of the meteorological parameters and the CPV system parameters are discussed. This is followed by a description of proposed multichannel data acquisition and logger for CPV technology. Experimental results have proven a good level of accuracy of the proposed system in terms of the acquired meteorological parameters and CPV system parameters.","PeriodicalId":325846,"journal":{"name":"2012 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126864576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A random switching method for PWM cascaded H-bridge multi-level inverter PWM级联h桥多电平逆变器的随机开关方法
2012 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2012-10-01 DOI: 10.1109/ICCIRCUITSANDSYSTEMS.2012.6408324
M. Mardaneh, Zhale Hashemi
{"title":"A random switching method for PWM cascaded H-bridge multi-level inverter","authors":"M. Mardaneh, Zhale Hashemi","doi":"10.1109/ICCIRCUITSANDSYSTEMS.2012.6408324","DOIUrl":"https://doi.org/10.1109/ICCIRCUITSANDSYSTEMS.2012.6408324","url":null,"abstract":"In this paper a modified pulse width modulation (PWM) method is proposed to reduce the switching losses in cascaded H-bridge (CHB) multi-level inverter. A random switching scheme is also utilized to overcome the problem of unequal switching loss in power switches.","PeriodicalId":325846,"journal":{"name":"2012 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116196176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Modular body sensor system design for plug-and-play monitoring system 模块化车身传感器系统设计,用于即插即用式监控系统
2012 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2012-10-01 DOI: 10.1109/ICCIRCUITSANDSYSTEMS.2012.6408278
M. Subakin, F. Hussin
{"title":"Modular body sensor system design for plug-and-play monitoring system","authors":"M. Subakin, F. Hussin","doi":"10.1109/ICCIRCUITSANDSYSTEMS.2012.6408278","DOIUrl":"https://doi.org/10.1109/ICCIRCUITSANDSYSTEMS.2012.6408278","url":null,"abstract":"Digital physiological monitoring is rapidly expanding day to day. Multiple types of sensors with unique specifications are designed to improve physiological monitoring. Many health problems can be detected in the early stages using this modern technology. To achieve this, many researchers around the world are doing some form of research in improving the health in general. In some cases, the root cause is unknown and in others the onset of a certain medical condition is important to be recognized. To do this, researchers build their own health monitoring system; this can be time consuming and takes away researchers time from doing the really needed tasks such as identifying and diagnosing the types of illness. Therefore, this paper illustrates a plug-and-play development tool for medical physiological monitoring that can easily be deployed for various health monitoring applications. Using modular plug and play system, the researchers do not have to spend weeks or months to design the complete system. The proposed system provides for a quick integration of many sensor modules with minor effort.","PeriodicalId":325846,"journal":{"name":"2012 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130403934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low-power high-gain 2.45-GHz CMOS dual-stage LNA with linearity enhancement 一种低功耗高增益的2.45 ghz CMOS双级线性放大器
2012 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2012-10-01 DOI: 10.1109/ICCIRCUITSANDSYSTEMS.2012.6408333
F. Eshghabadi, H. A. Eshghabadi, N. Noh, M. T. Mustaffa, A. A. Manaf, O. Sidek
{"title":"A low-power high-gain 2.45-GHz CMOS dual-stage LNA with linearity enhancement","authors":"F. Eshghabadi, H. A. Eshghabadi, N. Noh, M. T. Mustaffa, A. A. Manaf, O. Sidek","doi":"10.1109/ICCIRCUITSANDSYSTEMS.2012.6408333","DOIUrl":"https://doi.org/10.1109/ICCIRCUITSANDSYSTEMS.2012.6408333","url":null,"abstract":"This paper presents a dual-stage LNA design which is enhanced for gain, linearity and noise figure under a certain power constraint. The LNA benefits from an inductively-degenerated cascode amplifier in the first stage which is followed by a common-source amplifier as the second stage. Two techniques are used to improve the linearity of this 24-dB gain LNA while maintaining the noise figure equal to 2 dB. An input 1-dB gain compression point of -21 dBm was achieved at 2.45-GHz operating frequency. The 0.13-μm CMOS LNA draws a 4-mA current from a 1.2-volt power supply.","PeriodicalId":325846,"journal":{"name":"2012 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121718839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Study on sulfate reducing bacteria detection using Adaptive Neuro-fuzzy Inference System 自适应神经模糊推理系统在硫酸盐还原菌检测中的应用研究
2012 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2012-10-01 DOI: 10.1109/ICCIRCUITSANDSYSTEMS.2012.6408335
U. Chandaran, Z. Abdul Halim, L. Sian
{"title":"Study on sulfate reducing bacteria detection using Adaptive Neuro-fuzzy Inference System","authors":"U. Chandaran, Z. Abdul Halim, L. Sian","doi":"10.1109/ICCIRCUITSANDSYSTEMS.2012.6408335","DOIUrl":"https://doi.org/10.1109/ICCIRCUITSANDSYSTEMS.2012.6408335","url":null,"abstract":"The detection of sulfate reducing bacteria (SRB) in a water system is very crucial to prevent the corrosion of iron material in the system. In this regard, a method of using an Adaptive Neuro-fuzzy Inference System (ANFIS) is studied for the modeling and detection of SRB in a medium. A study on ANFIS concept is made to further understand the structure and criteria of the system. The experimental data obtained from data acquisition board are used for training of the ANFIS system. Three parameters (voltage, temperature and humidity) are selected as major factors in determining existence of the bacteria. Two membership functions (trapezoidal and bell-shaped) are used for training the data. The results show that ANFIS with trapezoidal membership function is the best with its average error, 1.66E-07 at epoch 250.","PeriodicalId":325846,"journal":{"name":"2012 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125047655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Implementation of the ultra-low power load-independent LC VCO 超低功耗负载无关型LC压控振荡器的实现
2012 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2012-10-01 DOI: 10.1109/ICCIRCUITSANDSYSTEMS.2012.6408299
D. Martynenko, G. Fischer, O. Klymenko
{"title":"Implementation of the ultra-low power load-independent LC VCO","authors":"D. Martynenko, G. Fischer, O. Klymenko","doi":"10.1109/ICCIRCUITSANDSYSTEMS.2012.6408299","DOIUrl":"https://doi.org/10.1109/ICCIRCUITSANDSYSTEMS.2012.6408299","url":null,"abstract":"In this paper the influence of the external load on the key parameters of the commonly used cross-coupled LC VCO architecture is investigated. It is shown, that even high ohmic external load decreases the impedance of the resonator, limits the frequency tuning range, degraded the phase noise and increases the power dissipation of the structure. Additionally, based on the carried out analyses, the novel load-independent LC VCO architecture is implemented and characterized. In the presented VCO topology, the resonator is isolated from the external load, by connecting the VCO outputs in the common collector configuration. As a result, the oscillator with the power consumption of 540 μW from the 1.8 supply voltage is achieved. The measured frequency tuning range of the VCO lies between 6.30 GHz and 8.59 GHz and the phase noise is better than -100 dBc/MHz at the frequency offset of 1 MHz within entire tuning range.","PeriodicalId":325846,"journal":{"name":"2012 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114825926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 0.9-V high-PSRR bandgap with self-cascode current mirror 带自级联码电流反射镜的0.9 v高psrr带隙
2012 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2012-10-01 DOI: 10.1109/ICCIRCUITSANDSYSTEMS.2012.6408273
Tianlin Cao, Yan Han, Xiaopeng Liu, Hao Luo, Lu Liao, Hao Zhang
{"title":"A 0.9-V high-PSRR bandgap with self-cascode current mirror","authors":"Tianlin Cao, Yan Han, Xiaopeng Liu, Hao Luo, Lu Liao, Hao Zhang","doi":"10.1109/ICCIRCUITSANDSYSTEMS.2012.6408273","DOIUrl":"https://doi.org/10.1109/ICCIRCUITSANDSYSTEMS.2012.6408273","url":null,"abstract":"A 0.9-V supply voltage, high power supply rejection ratio (high-PSRR) bandgap reference with high-order compensation is presented. By inserting a group of self-cascode current mirrors and adopting an effective technique of high-order compensation, this bandgap reference is designed in 0.18 μm CMOS process. Simulation has been carried out and the results prove that the PSRR and temperature coefficient (TC) are both improved evidently in low voltage. Under 0.9 V supply voltage, the bandgap reference's PSRR is -86 dB at 1 kHz and -25 dB at 1 MHz, its TC is 0.096 ppm/°C from -40 °C to +85 °C, consuming a total current of 86.6 μA.","PeriodicalId":325846,"journal":{"name":"2012 IEEE International Conference on Circuits and Systems (ICCAS)","volume":" 23","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120830971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A low power programmable frequency divider intended for frequency synthesizer designed in accordance with IEEE 802.15.4a standard 一种低功耗可编程分频器,用于按照IEEE 802.15.a标准设计的频率合成器
2012 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2012-10-01 DOI: 10.1109/ICCIRCUITSANDSYSTEMS.2012.6408300
D. Martynenko, G. Fischer, O. Klymenko
{"title":"A low power programmable frequency divider intended for frequency synthesizer designed in accordance with IEEE 802.15.4a standard","authors":"D. Martynenko, G. Fischer, O. Klymenko","doi":"10.1109/ICCIRCUITSANDSYSTEMS.2012.6408300","DOIUrl":"https://doi.org/10.1109/ICCIRCUITSANDSYSTEMS.2012.6408300","url":null,"abstract":"A low power programmable frequency divider for IEEE 802.15.4a standard is implemented in a 0.25 μm BiCMOS process. The frequency divider architecture is based on the low power high speed triple-modulus prescaler design. The triple-modulus prescaler supports three division modes (N/N±1) via the phase switching between the output signals of the master/slave emitter-coupled logic divide-by-two stage. The novel N-1 division mode is achieved by modifying the low frequency phase selection control logic. The wide division range is achieved by cascading the prescalers. In addition, the 50% duty cycle baseband clock is derived from the divider chain. The frequency of the baseband clock is equal to 499.2 MHz regardless of the chosen center frequency (in combination with the corresponding division ratio) for the multi-channel system designed for IEEE 802.15.4a standard. The measured maximum input frequencies of the divider for each of the required division ratio prove that the presented divider satisfies the specification. The measurement results demonstrate that the presented frequency divider can be used in the frequency synthesizer for generation of the center frequencies for multi-channel transceiver designed in accordance to IEEE 802.15.4a standard. The measured power dissipation of the programmable frequency divider is equal to 31.2 mW from 2.6 V supply voltage.","PeriodicalId":325846,"journal":{"name":"2012 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127969096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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