带自级联码电流反射镜的0.9 v高psrr带隙

2012 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2012-10-01 DOI:10.1109/ICCIRCUITSANDSYSTEMS.2012.6408273

Tianlin Cao, Yan Han, Xiaopeng Liu, Hao Luo, Lu Liao, Hao Zhang

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引用次数: 13

摘要

提出了一种具有高阶补偿的0.9 v电源电压、高电源抑制比(high psrr)带隙基准电路。通过插入一组自级联电流镜，采用有效的高阶补偿技术，设计了0.18 μm CMOS制程的带隙基准电路。仿真结果表明，在低电压下，PSRR和温度系数(TC)均有明显提高。在0.9 V电源电压下，带隙基准的PSRR在1 kHz时为-86 dB，在1 MHz时为-25 dB，在-40°C至+85°C范围内的TC为0.096 ppm/°C，总电流消耗为86.6 μA。

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A 0.9-V high-PSRR bandgap with self-cascode current mirror

A 0.9-V supply voltage, high power supply rejection ratio (high-PSRR) bandgap reference with high-order compensation is presented. By inserting a group of self-cascode current mirrors and adopting an effective technique of high-order compensation, this bandgap reference is designed in 0.18 μm CMOS process. Simulation has been carried out and the results prove that the PSRR and temperature coefficient (TC) are both improved evidently in low voltage. Under 0.9 V supply voltage, the bandgap reference's PSRR is -86 dB at 1 kHz and -25 dB at 1 MHz, its TC is 0.096 ppm/°C from -40 °C to +85 °C, consuming a total current of 86.6 μA.

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来源期刊

2012 IEEE International Conference on Circuits and Systems (ICCAS)

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