2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI)最新文献

SDDS-NCL design: Analysis of supply voltage scaling SDDS-NCL设计:电源电压缩放分析

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2800999

R. Guazzelli, F. Moraes, Ney Laert Vilar Calazans, Matheus T. Moreira

引用次数: 2

CMOS transconductor analysis for low temperature sensitivity based on ZTC MOSFET condition 基于ZTC MOSFET条件的CMOS晶体管低温灵敏度分析

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2801000

P. Toledo, H. Klimach, D. Cordova, S. Bampi, E. Fabris

{"title":"CMOS transconductor analysis for low temperature sensitivity based on ZTC MOSFET condition","authors":"P. Toledo, H. Klimach, D. Cordova, S. Bampi, E. Fabris","doi":"10.1145/2800986.2801000","DOIUrl":"https://doi.org/10.1145/2800986.2801000","url":null,"abstract":"The necessary conditions to design MOSFET transconductors with low temperature dependence are analysed and defined in this paper. Transconductors, or Gm circuits, are fundamental blocks used to implement adjustable filters, multipliers, controlled oscillators, amplifiers and a large variety of analog circuits. Temperature stability is a must in such applications, and herein we show a strategy that can be used to improve the temperature stability of these transconductors by biasing MOSFETs at transconductance zero-temperature condition (GZTC). This special bias condition is analysed using a MOSFET model which is continuous from weak to strong inversion, and it is proved that this condition always occurs from moderate to strong inversion operation in any CMOS fabrication process. Additionally, a few example circuits are proposed using this technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits were simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/°C.","PeriodicalId":325572,"journal":{"name":"2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132649685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Design and optimization of high sensitivity transimpedance amplifiers in 130 nm CMOS and BiCMOS technologies for high speed optical receivers 高速光接收机用130 nm CMOS和BiCMOS技术高灵敏度跨阻放大器的设计与优化

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2801001

A. F. Ponchet, E. M. Bastida, R. Panepucci, J. Swart, C. Finardi

引用次数: 6

A 25-dBm 1-GHz power amplifier integrated in CMOS 180nm for wireless power transferring 一种集成在180nm CMOS中的25dbm 1ghz功率放大器，用于无线电力传输

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2800989

F. L. Cabrera, F. Sousa

引用次数: 10

Direct feedback topology for reducing residual voltage in functional electrical stimulation 用于降低功能性电刺激中残余电压的直接反馈拓扑结构

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2801006

Lucas Teixeira, C. Rodrigues, C. Prior

{"title":"Direct feedback topology for reducing residual voltage in functional electrical stimulation","authors":"Lucas Teixeira, C. Rodrigues, C. Prior","doi":"10.1145/2800986.2801006","DOIUrl":"https://doi.org/10.1145/2800986.2801006","url":null,"abstract":"Implantable functional electric stimulation (FES) systems are currently being investigated as treatment for some types of neural dysfunctions. For this purpose, several neural stimulator systems on a chip (SOCs) have been proposed for: deep brain stimulation (DBS), cochlear prosthesis, visual prosthesis (VP), and artificial limbs control. Two major and related issues in FES are the charge balancing and Faradaic currents. When stimulation currents have DC components, or if residual voltage persists accross electrodes, the accumulated electronic charge is converted into ionic species, thus feeding irreversible Faradaic reactions that damage electrodes and necrose tissues. This article introduces circuit solutions for balancing functional electrical stimulation whilst reducing residual voltages at electrodes. The circuit consists of four blocks: an ultra-low-power charge-redistribution digital-to-analog converter (CR-DAC), a feedback mechanism, a high-voltage H-bridge and a digital controller. To prove the effectiveness of the proposed topology a circuit is being designed in CMOS UMC 130nm technology, and simulation results suggest that proposed technique allows to keep electrode voltage under safe limits, smaller than 28mV.","PeriodicalId":325572,"journal":{"name":"2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125077656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High PSRR nano-watt MOS-only threshold voltage monitor circuit 高PSRR纳瓦mos阈值电压监测电路

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2801009

Jhon A. Gomez C., H. Klimach, E. Fabris, O. E. Mattia

{"title":"High PSRR nano-watt MOS-only threshold voltage monitor circuit","authors":"Jhon A. Gomez C., H. Klimach, E. Fabris, O. E. Mattia","doi":"10.1145/2800986.2801009","DOIUrl":"https://doi.org/10.1145/2800986.2801009","url":null,"abstract":"This work presents a high PSRR nano-watt resistorless threshold voltage (VT0) monitor circuit that can be used in temperature sensors, voltage and current references, radiation dosimeters and other applications such as fabrication process monitoring and verification. In this circuit design the MOS transistors operate in subthreshold and near-threshold regimes, the circuit analysis is based on a current-voltage relationship derived from a continuous physical MOSFET model, valid from weak to strong inversion. The bias condition is established from the equilibrium between two self-cascode cells operating at different inversion levels, and the high PSRR results from a high gain feedback path. The circuit is MOSFET-only, and can be implemented in any standard digital CMOS process. Post-layout simulations show that it operates with less than 1 V of power supply, consuming only tens of nW, and resulting in a VT0 error lower than 1%, when compared to its modeling value, for a -40 to +125°C temperature range. A very high rejection to VDD variation is achieved in this design, with PSRR lower than -63.9 dB at 100 Hz, and a line sensitivity lower than 252 ppm/V was found for a supply range from 1 V to 3 V. Monte-Carlo simulations are presented to evaluate the fabrication variability sensitivity, presenting a maximum error of 4% for a 3σ spread range. The circuit area is very small, around 0.0047 mm2 including the start-up stage.","PeriodicalId":325572,"journal":{"name":"2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127434309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

A 2-decades wideband low-noise amplifier with high gain and ESD protection 具有高增益和ESD保护的20年宽带低噪声放大器

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2800990

A. L. T. Costa, H. Klimach, S. Bampi

{"title":"A 2-decades wideband low-noise amplifier with high gain and ESD protection","authors":"A. L. T. Costa, H. Klimach, S. Bampi","doi":"10.1145/2800986.2800990","DOIUrl":"https://doi.org/10.1145/2800986.2800990","url":null,"abstract":"This work presents a 2-decades wideband (15.5 MHz-1.55 GHz) low-noise amplifier (LNA) circuit. As its wideband range extends from HF to UHF, it includes, among others, the ISM bands (27.12 MHz, 40.7MHz, 434.79 MHz, 928 MHz), the GSM850 and GSM900 bands, and IEEE 802.22 WRAN bands (54 MHz-862 MHz). The proposed circuit operates also as a balun (single-ended input - differencial output) and its layout presents a very small area, an important savings resulting from this inductorless design for the LNA. An auxiliary amplifier was introduced so that a high gain and a high IIP3 can be achieved with low Noise Figure (NF). The linearity was improved using a distortion cancellation strategy and the NF was improved through a noise canceling technique. The amplifier was implemented in a 130 nm CMOS process, using a PDK from Silterra foundry, in a compact 77μm × 54μm core area. Simulations including post-layout parasitics, bondwire, ESD protection and PAD input parasitics resulted (over the entire band) in a voltage gain of 20.8-24.9 dB, a noise figure (NF) of 2.7-3.7 dB, an input power reflection coefficient Sn <; -11.4 dB, an input third-order intercept point (IIP3) = -0.4 dBm (@750MHz), and a power consumption of 10.4 mW under 1.2 V supply. This balun LNA shows a worst case gain imbalance between outputs of 1.2 dB and very low sensitivity to temperature variations for gain, NF and Sn in the range of 0 to 85°C.","PeriodicalId":325572,"journal":{"name":"2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"229 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132494031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A phase shifting multiple filter design methodology for Lucy-Richardson deconvolution of log-mixtures complex RTN tail distribution 对数混合复RTN尾分布Lucy-Richardson反褶积的相移多重滤波器设计方法

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2800996

H. Yamauchi, Worawit Somha

引用次数: 1

Wideband low noise variable gain amplifier 宽带低噪声变增益放大器

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2801029

F. D. Baumgratz, Hao Li, S. Bampi, C. Saavedra

引用次数: 6

System-level design of single-bit sigma-delta modulators based on MSA and SNR data graphics 基于MSA和信噪比数据图形的单比特σ - δ调制器系统级设计

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2801028

R. Viera, Jorge V. de la Cruz, A. Aita, C. Prior, J. B. Martins

引用次数: 0