2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI)最新文献_第2页

Designing CMOS for near-threshold minimum-energy operation and extremely wide V-F scaling 设计近阈值最小能量操作和极宽V-F缩放的CMOS

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2801004

Andre Luis Rodeghiero Rosa, L. Soares, Kleber Stangherlin, S. Bampi

{"title":"Designing CMOS for near-threshold minimum-energy operation and extremely wide V-F scaling","authors":"Andre Luis Rodeghiero Rosa, L. Soares, Kleber Stangherlin, S. Bampi","doi":"10.1145/2800986.2801004","DOIUrl":"https://doi.org/10.1145/2800986.2801004","url":null,"abstract":"This work proposes a strategy for designing VLSI circuits to operate in an extremely wide Voltage-Frequency Scaling (VFS) range, from the supply voltage at which the minimum energy per operation (MEP) is achieved, up to the nominal voltage for the process. First the sizing methodology of two library cells using transistors with different threshold voltages: Regular-VT (RVT) and Low-VT (LVT) is described. Just five combinational cells: INV, NAND, NOR, OAI21, and AOI22 comprise the libraries plus two register cells, all with multiple strengths, for RVT ones. The sizing rule for the transistors of each cell is directly driven by requiring equal rise and fall times in order to attenuate variability effects at very low supply voltages. These cell libraries were characterized for typical, fast, and slow process corners, over temperature (-40°C, 25°C, and 125°C) variations, and for supply voltages varying from 200 mV up to 1.2 V with small supply steps. Circuit syntheses were performed for ten VLSI circuit benchmarks: notch filter, 8051 compatible core, and eight ISCAS benchmark circuits, considering all VDD operating points. We show that at the optimum MEP point (near-VT) an average reduction of 54.46% and 99.01% in energy is possible, when compared with deep sub-threshold and nominal supply voltages, respectively, at room temperature. The extremely wide VFS regime enables operating frequencies varying from hundreds of kHz up to MHz/GHz at -40°C and 25°C, and from MHz up to GHz at 125°C. The near-VT designs herein presented, when compared to related work, showed on average an energy reduction and performance gain of 24.1% and 152.68%, respectively, for the same circuit benchmarks. Comparison of near-VT operation at very low and high temperatures show advantages for a hotter CMOS operation for this regime.","PeriodicalId":325572,"journal":{"name":"2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122878379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

PHiCIT — Improving hierarchical Networks-on-Chip through 3D silicon photonics integration 通过三维硅光子学集成改进分层片上网络

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2801022

C. Reinbrecht, Martha Johanna Sepúlveda, A. Susin

{"title":"PHiCIT — Improving hierarchical Networks-on-Chip through 3D silicon photonics integration","authors":"C. Reinbrecht, Martha Johanna Sepúlveda, A. Susin","doi":"10.1145/2800986.2801022","DOIUrl":"https://doi.org/10.1145/2800986.2801022","url":null,"abstract":"The Network-on-Chip (NoC) architecture has been seen as an interconnect solution for complex systems. However, performance and energy issues still represent limiting factors for Multi-Processors Systems-on-Chip (MPSoC). In order to match low power and high performance, hierarchical NoCs have been proposed, with interconnecting clusters of IPs tailored to application specific domains. In the near future however, this methodology will be limited by the long wires for global connection. In this paper, we present an optimized hierarchical network-on-chip, the PHiCIT (Photonic Hierarchical Crossbar-based Interconnection Three-dimensional architecture). This architecture proposal aims to maximize the overall performance by using three levels of interconnection: photonic crossbars for intra-cluster communication, traditional electric routers for the inter-cluster communication, and 3D technology to explore power and area optimization. Experimental results show that PHiCIT can reduce the latency against a pure electrical mesh NoC by up to 47%, against an electric hierarchical NoC by up to 6%, and against a photonic mesh NoC by up to 34%, considering PARSEC benchmark applications.","PeriodicalId":325572,"journal":{"name":"2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127771547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Memory-aware and high-throughput hardware design for the HEVC fractional motion estimation HEVC分数运动估计的内存感知和高吞吐量硬件设计

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2801017

Vladimir Afonso, Henrique Maich, Luan Audibert, B. Zatt, M. Porto, L. Agostini

引用次数: 14

Low power, high-sensitivity clock recovery circuit for LF/HF RFID applications 低功耗，高灵敏度时钟恢复电路，用于低频/高频RFID应用

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2801015

Rafael Cantalice, A. Simionovski, F. P. Cortes, M. Lubaszewski

引用次数: 0

MCML gate design for standard cell library 标准单元库的MCML栅极设计

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2801016

Bruno Canal, Cicero Nunes, R. Ribas, E. Fabris

引用次数: 0

0.5 V supply voltage reference based on the MOSFET ZTC condition 基于MOSFET ZTC条件的0.5 V电源参考电压

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2800988

D. Cordova, P. Toledo, H. Klimach, S. Bampi, E. Fabris

{"title":"0.5 V supply voltage reference based on the MOSFET ZTC condition","authors":"D. Cordova, P. Toledo, H. Klimach, S. Bampi, E. Fabris","doi":"10.1145/2800986.2800988","DOIUrl":"https://doi.org/10.1145/2800986.2800988","url":null,"abstract":"The continuous scaling of CMOS devices has required the consequent reduction of the supply voltages. There is a need for analog and RF circuits able to operate under at supplies lower than 0.5 V. This paper presents a voltage reference based on the MOSFET zero-temperature condition (ZTC) that operates with a low 0.5 V supply. The circuit is composed by a diode-connected MOS transistor operating near the ZTC condition that is biased by a proportional-to-absolute-temperature (PTAT) current reference implemented with Schottky-diodes. The ZTC condition is analysed using a continuous MOSFET model that is valid from weak to strong inversion and the circuit behaviour is described by theoretical expressions. Our reference circuit is designed for 3 versions: each with MOSFETs of different threshold voltage (standard-VT, low-VT, and zero-VT), all available in the 130 nm CMOS process used. These designs result in three different and very low reference voltages: 312, 237, and 51 mV. All 3 designed reference operate in the range of 0.45 to 1.2 V of supply voltages, consuming 1 uA of typical supply current. Post-layout simulations present a Temperature Coefficients (TCs) of 214, 372, and 953 ppm/°C in a temperature range from -55 to 125°C, respectively. Monte-Carlo simulations show the fabrication variability impact on the circuit performance. The voltage reference was designed in a 130 nm process and it uses 0.014 mm2 of silicon area.","PeriodicalId":325572,"journal":{"name":"2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134604223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Minimization and encoding of high performance asynchronous state machines based on genetic algorithm 基于遗传算法的高性能异步状态机的最小化与编码

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2801018

T. Curtinhas, T. Cavalcante, D. L. Oliveira, L. Faria, O. Saotome

{"title":"Minimization and encoding of high performance asynchronous state machines based on genetic algorithm","authors":"T. Curtinhas, T. Cavalcante, D. L. Oliveira, L. Faria, O. Saotome","doi":"10.1145/2800986.2801018","DOIUrl":"https://doi.org/10.1145/2800986.2801018","url":null,"abstract":"Today, the design of complex synchronous digital systems shows serious difficulties relating to the global clock and to Deep-Sub-Micron MOS technology. The asynchronous design is an interesting alternative to solve these difficulties, once they do not present clock skew or distribution problems. However, the lack of tools for automatic synthesis is still a major drawback. Asynchronous Finite State Machines (AFSM) are widely used in the control of asynchronous digital systems. A very popular machine is the burst-mode Huffman machine (BM_HM), which accepts burst-mode specification is implemented as Huffman machines (HM). HM architecture, when compared to HM architecture with fed-back output, has advantages such as a better interaction with fast environments, reducing the cost of timing analysis, and a lower latency time. As disadvantage, the area tends to be bigger. This paper proposes two novel algorithms based on genetic algorithms for the minimization and assignment of states, which are important steps in the synthesis of BM_HMs. These two algorithms were implemented in SAGAAs tool, which was tested in an extensive set of benchmarks, showing a high efficiency when compared to Minimalist tool that is state-of-the-art. It achieved an average reduction of 5.91% in the number of products, 15.50% in the number of literals and 32.61% in the total processing time. Our approach presents a low penalty of 1.56% and 4.41% in the number of states and in number of inserted state variables.","PeriodicalId":325572,"journal":{"name":"2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"177 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132624351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Run-time cache configuration for the LEON-3 embedded processor LEON-3嵌入式处理器的运行时缓存配置

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2801026

B. A. Silva, Lucas Albers Cuminato, Vanderlei Bonato, P. Diniz

引用次数: 7

Design of high-voltage level shifters based on stacked standard transistors for a wide range of supply voltages 基于堆叠标准晶体管的宽电压范围高压电平移位器的设计

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2801003

Sara Pashmineh, D. Killat

引用次数: 2

Analysis and system-level design of a high resolution incremental ΣΔ ADC for biomedical applications 用于生物医学应用的高分辨率增量ΣΔ ADC的分析和系统级设计

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2800998

A. W. A. Soares, D. Belfort, S. Catunda, R. Freire

引用次数: 1