R. Lababidi, F. Roy, D. L. Jeune, A. Mansour, J. Lintignat, A. Louzir
{"title":"Highly integrated active dual response filter","authors":"R. Lababidi, F. Roy, D. L. Jeune, A. Mansour, J. Lintignat, A. Louzir","doi":"10.1145/2800986.2801019","DOIUrl":"https://doi.org/10.1145/2800986.2801019","url":null,"abstract":"This work focuses on the design of a novel compact Active Dual Response Filter within a single device which allows ensuring the coexistence of three different standards while proposing an optimal structure in terms of response and space. The proposed filter is based on a highly selective low-pass filter at which a highly integrated compact notch filter is coupled. This co-integration of both filters is not a cascade so that the dual response filter occupies the same area as the low-pass filter alone. The Notch filter is set to 700 MHz and is loaded by an Active Capacitor (AC) circuit that allows a rejection at the notch central frequency of at least 19 dB. The low-pass filter cut-off frequency is Fc =890 MHz, the in band return loss is better than 20 dB. This methodology can be extended to various shapes of filter functions.","PeriodicalId":325572,"journal":{"name":"2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115944482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A low-area and high-throughput intra prediction architecture for a multi-standard HEVC and H.264/AVC video encoder","authors":"M. Corrêa, M. Porto, B. Zatt, L. Agostini","doi":"10.1145/2800986.2800994","DOIUrl":"https://doi.org/10.1145/2800986.2800994","url":null,"abstract":"This paper describes a low-area and high-throughput hardware architecture for the intra prediction coding of today's most important video coding standards - the state of the art HEVC and its predecessor H.264/AVC. In order to reduce control complexity, memory accesses and total area, our design works with a subset of the prediction modes and possible block sizes. The multi-standard strategy is desirable because most devices produced prior the HEVC release may only have H.264/AVC accelerators (most of handheld devices, digital TVs, and set-top-boxes). The architecture was fully described in VHDL and synthesized targeting an Altera Stratix V FPGA device. The architecture is capable of processing 2560×1600 videos at 33 frames per second when operating in HEVC mode, and 3840×2160 videos at 45 frames per second in H.264/AVC mode. The cost and performance results achieved are very satisfactory when compared to related works in the literature.","PeriodicalId":325572,"journal":{"name":"2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132948076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}