A low-area and high-throughput intra prediction architecture for a multi-standard HEVC and H.264/AVC video encoder

This paper describes a low-area and high-throughput hardware architecture for the intra prediction coding of today's most important video coding standards - the state of the art HEVC and its predecessor H.264/AVC. In order to reduce control complexity, memory accesses and total area, our design works with a subset of the prediction modes and possible block sizes. The multi-standard strategy is desirable because most devices produced prior the HEVC release may only have H.264/AVC accelerators (most of handheld devices, digital TVs, and set-top-boxes). The architecture was fully described in VHDL and synthesized targeting an Altera Stratix V FPGA device. The architecture is capable of processing 2560×1600 videos at 33 frames per second when operating in HEVC mode, and 3840×2160 videos at 45 frames per second in H.264/AVC mode. The cost and performance results achieved are very satisfactory when compared to related works in the literature.