2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI)最新文献_第4页

Optimum operating points of transistors with minimal aging-aware sensitivity 具有最小老化敏感的晶体管的最佳工作点

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2801021

Nico Hellwege, N. Heidmann, S. Paul, D. Peters-Drolshagen

引用次数: 5

Real-time architecture for HEVC motion compensation sample interpolator for UHD videos 用于超高清视频的HEVC运动补偿采样插值器的实时架构

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2801024

Wagner Penny, Guilherme Paim, M. Porto, L. Agostini, B. Zatt

引用次数: 9

Increasing observability in post-silicon debug using asymmetric Omega Networks 使用非对称Omega网络增加后硅调试中的可观察性

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2801011

A. M. Gomes, F. Alves, R. Ferreira, J. A. Nacif

{"title":"Increasing observability in post-silicon debug using asymmetric Omega Networks","authors":"A. M. Gomes, F. Alves, R. Ferreira, J. A. Nacif","doi":"10.1145/2800986.2801011","DOIUrl":"https://doi.org/10.1145/2800986.2801011","url":null,"abstract":"Current pre-silicon verification techniques can not guarantee error free designs for complex integrated circuits during their first fabrication. Some errors are only uncovered when the device is running at full clock speed. Using post-silicon debug techniques, the designer can monitor the device capturing errors that occur only after millions of clock cycles. However, in order to identify the cause of the error, the signals must be stored in a trace buffer memory, dumped, and then analyzed. Thus, the trace buffer size limits the number of analyzed signals, forcing the designer to select a signal subset to monitor from all tapped signals. In this paper, we propose a novel asymmetric network, based on the traditional Omega Network. We propose to use this network as an interconnection fabric to connect the monitored signals to the trace buffer. We compare the Asymmetric Omega Network performance to the Mux Tree Network, which is adopted by industry as the standard solution to interconnect signals for post-silicon debug. We show that our Asymmetric Omega Network is ≈ 4.6 times more effective reducing the blocking rate at the cost of ≈ 21% area overhead compared to Mux Trees.","PeriodicalId":325572,"journal":{"name":"2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122684749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

0.5 V supply resistorless voltage reference for low voltage applications 0.5 V电源无电阻电压参考低压应用

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2800987

V. RenatoCampana, H. Klimach, S. Bampi

引用次数: 7

Optimization methodology for a 460-MHz-GBW and 80-dB-SNR low-power current-mode amplifier 460 mhz - gbw和80 db - snr低功率电流模式放大器的优化方法

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2801020

Pietro M. Ferreira, A. Kolar, P. Bénabès

引用次数: 0

Design of 28 nm CMOS integrated transformers for a 60 GHz power amplifier 用于60 GHz功率放大器的28 nm CMOS集成变压器设计

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2801002

B. Leite, E. Kerhervé, D. Belot

引用次数: 0

Power-aware design of electronic system level using interoperation of hybrid and distributed simulations 基于混合与分布式仿真互操作的电子系统级功耗感知设计

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2801023

H. F. A. Oliveira, A. Brito, E. Melcher, Harald Bucher, J. M. F. R. Araújo, Liana Duenha

{"title":"Power-aware design of electronic system level using interoperation of hybrid and distributed simulations","authors":"H. F. A. Oliveira, A. Brito, E. Melcher, Harald Bucher, J. M. F. R. Araújo, Liana Duenha","doi":"10.1145/2800986.2801023","DOIUrl":"https://doi.org/10.1145/2800986.2801023","url":null,"abstract":"Power consumption is a big challenge in chip design. Decisions taken in early design phases have large impact on the power consumption. Generally, simulation-based Design Space Exploration (DSE) is computationally costly for large problems due the size of design space. Simulate the possible scenarios in a distributed fashion can decrease the time to find efficient solutions. In this paper we describe an approach using HLA (High level Architecture) that allows to distribute and simulate different scenarios of Electronic System Level (ESL) models and/or Register Transfer Level (RTL) models for collecting and grouping power estimation data in a centralized manner. These models can be described in C++, SystemC, SystemVerilog or Verilog. As case study, we use a benchmark composed of a scalable set of MPSoCs described in C++/SystemC. We also use a small project in SystemVerilog/Verilog to validate the power estimation data collecting from models described in these languages through the approach. The experimental results show that the proposed method can distribute and simulate different scenarios of Electronic System Level (ESL) models as well as Register Transfer Level (RTL) models and provide a unified view of power estimation data.","PeriodicalId":325572,"journal":{"name":"2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"9 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130160654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Differential evolution to reduce energy consumption in three-level memory hierarchy 基于差分进化的三层内存结构能耗降低算法

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2801005

A. Silva-Filho, L. Nunes, Henrique F. Lacerda

{"title":"Differential evolution to reduce energy consumption in three-level memory hierarchy","authors":"A. Silva-Filho, L. Nunes, Henrique F. Lacerda","doi":"10.1145/2800986.2801005","DOIUrl":"https://doi.org/10.1145/2800986.2801005","url":null,"abstract":"This paper presents an improved differential evolution (DE) algorithm for multi-objective optimization in the discrete domain, applied to a cache memory hierarchy exploration problem, aiming to reduce the energy consumption and to increase the performance to process an embedded application. The architecture exploration is based on cache parameters adjustments and the memory hierarchy is composed of three levels of cache memory. A model of LPDDR2 memory (Low Power DDR2) was adopted to simulate the main memory and a recent cache memory model based on 32 nm transistor technology was used. In these experiments, the proposed algorithm was applied to nine different applications from the MiBench and the MediaBenchII suites. Furthermore, the performance of the proposed strategy was compared with those of SPEA2 and NSGAII optimization mechanisms. The metrics selected to compare the quality of the Pareto front found for each of those algorithms were the hypervolume and the generational distance. The results show that the proposed strategy based on DE optimization algorithm applied to memory hierarchy exploration problem obtained better results for both indicators, achieving improvements in 100% and 78% of cases in both metrics mentioned respectively.","PeriodicalId":325572,"journal":{"name":"2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121264509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Reconfigurable group-wise security architecture for NoC-based MPSoCs protection 可重构的组安全架构，用于基于noc的mpsoc保护

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2801025

Martha Johanna Sepúlveda, Daniel Flórez, G. Gogniat

{"title":"Reconfigurable group-wise security architecture for NoC-based MPSoCs protection","authors":"Martha Johanna Sepúlveda, Daniel Flórez, G. Gogniat","doi":"10.1145/2800986.2801025","DOIUrl":"https://doi.org/10.1145/2800986.2801025","url":null,"abstract":"Applications are spread into the computational resources of the Multi-processors Systems-on-Chip (MPSoCs) to enhance the performance. This approach forces the peer interaction of different IPs, turning vulnerable applications characterized by security requirements. Sensitive traffic can be protected by implementing security domains, whose aim is to wrap sensitive IPs. Networks-on-Chip can be enhanced in order to provide security services for the data exchanged among the group of IPs that host the sensitive application tasks. While firewalls approaches only guarantee continuous security domains, establishing disrupted domains at MPSoCs demands lightweight cryptographic techniques. In this work we propose a NoC-based architecture able to implement dynamically disrupted security zones by means of two group-wise cryptographic techniques: Diffie-Hellman and mapping-aware key pre-distribution scheme. For the first time we explore the impact of these two approaches on the MPSoC performance. We show that our architecture is able to efficiently manage dynamic security domains while presenting low impact on the performance and cost of MPSoCs.","PeriodicalId":325572,"journal":{"name":"2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121446174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Jezz: An effective legalization algorithm for minimum displacement 一个有效的最小位移合法化算法

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2015-08-31 DOI: 10.1145/2800986.2801013

Julia Casarin Puget, G. Flach, M. Johann, R. Reis

引用次数: 21