Direct feedback topology for reducing residual voltage in functional electrical stimulation

Abstract

Implantable functional electric stimulation (FES) systems are currently being investigated as treatment for some types of neural dysfunctions. For this purpose, several neural stimulator systems on a chip (SOCs) have been proposed for: deep brain stimulation (DBS), cochlear prosthesis, visual prosthesis (VP), and artificial limbs control. Two major and related issues in FES are the charge balancing and Faradaic currents. When stimulation currents have DC components, or if residual voltage persists accross electrodes, the accumulated electronic charge is converted into ionic species, thus feeding irreversible Faradaic reactions that damage electrodes and necrose tissues. This article introduces circuit solutions for balancing functional electrical stimulation whilst reducing residual voltages at electrodes. The circuit consists of four blocks: an ultra-low-power charge-redistribution digital-to-analog converter (CR-DAC), a feedback mechanism, a high-voltage H-bridge and a digital controller. To prove the effectiveness of the proposed topology a circuit is being designed in CMOS UMC 130nm technology, and simulation results suggest that proposed technique allows to keep electrode voltage under safe limits, smaller than 28mV.