A 25-dBm 1-GHz power amplifier integrated in CMOS 180nm for wireless power transferring

Abstract

This paper presents the design of a power amplifier integrated in a CMOS 180 nm technology, which is intended to drive an inductive link operating at 990 MHz. A class-D topology is employed to avoid the use of inductors. A design methodology is proposed to find the optimal transistor width, solving the trade-off between the ON-resistance and gate capacitance. The area occupied is 1.5 mm2, most of it is used by the PADs and the wide interconnects. Post-layout simulations showed a power efficiency of 58% when delivering 25.1 dBm to the primary inductor of a wireless power transferring system.