SDDS-NCL design: Analysis of supply voltage scaling

Abstract

Despite their substantial power savings, voltage scaling design increases the concern about sensitivity to manufacturing process and operating conditions variations. These can induce significant delay changes in fabricated circuits. An elegant approach to cope with these issues is to employ quasi delay-insensitive asynchronous design styles, which allow relaxing timing assumptions, enabling simpler timing closure when compared to clocked solutions. This work explores the effects of supply voltage scaling on a specific class of quasi-delay-insensitive circuits called spatially distributed dual spacer null convention logic (SDDS-NCL). It first analyzes basic SDDS-NCL gates from a 65 nm cell library. The analysis explores the effects of supply voltage scaling on isolated cells, encompassing static power, energy and delay trade-offs. Next, it shows the results of a similar analysis applied to a 324-cell case study circuit. Results indicate that the evaluated class of circuits can significantly benefit from sub- and near-threshold operation to trade off energy efficiency and performance.