{"title":"一种集成在180nm CMOS中的25dbm 1ghz功率放大器，用于无线电力传输","authors":"F. L. Cabrera, F. Sousa","doi":"10.1145/2800986.2800989","DOIUrl":null,"url":null,"abstract":"This paper presents the design of a power amplifier integrated in a CMOS 180 nm technology, which is intended to drive an inductive link operating at 990 MHz. A class-D topology is employed to avoid the use of inductors. A design methodology is proposed to find the optimal transistor width, solving the trade-off between the ON-resistance and gate capacitance. The area occupied is 1.5 mm2, most of it is used by the PADs and the wide interconnects. Post-layout simulations showed a power efficiency of 58% when delivering 25.1 dBm to the primary inductor of a wireless power transferring system.","PeriodicalId":325572,"journal":{"name":"2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"A 25-dBm 1-GHz power amplifier integrated in CMOS 180nm for wireless power transferring\",\"authors\":\"F. L. Cabrera, F. Sousa\",\"doi\":\"10.1145/2800986.2800989\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design of a power amplifier integrated in a CMOS 180 nm technology, which is intended to drive an inductive link operating at 990 MHz. A class-D topology is employed to avoid the use of inductors. A design methodology is proposed to find the optimal transistor width, solving the trade-off between the ON-resistance and gate capacitance. The area occupied is 1.5 mm2, most of it is used by the PADs and the wide interconnects. Post-layout simulations showed a power efficiency of 58% when delivering 25.1 dBm to the primary inductor of a wireless power transferring system.\",\"PeriodicalId\":325572,\"journal\":{\"name\":\"2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI)\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-08-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/2800986.2800989\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/2800986.2800989","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 25-dBm 1-GHz power amplifier integrated in CMOS 180nm for wireless power transferring
This paper presents the design of a power amplifier integrated in a CMOS 180 nm technology, which is intended to drive an inductive link operating at 990 MHz. A class-D topology is employed to avoid the use of inductors. A design methodology is proposed to find the optimal transistor width, solving the trade-off between the ON-resistance and gate capacitance. The area occupied is 1.5 mm2, most of it is used by the PADs and the wide interconnects. Post-layout simulations showed a power efficiency of 58% when delivering 25.1 dBm to the primary inductor of a wireless power transferring system.
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