Joohee Kim, Jonghyun Cho, J. Pak, Joungho Kim, J. Yook, J. C. Kim
{"title":"High-frequency through-silicon Via (TSV) failure analysis","authors":"Joohee Kim, Jonghyun Cho, J. Pak, Joungho Kim, J. Yook, J. C. Kim","doi":"10.1109/EPEPS.2011.6100237","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100237","url":null,"abstract":"Despite the many advantages of 3D ICs, the yield loss experienced during the 3D IC fabrication process limits the commercialization of 3D IC products. In this study, we propose a novel method for TSV failure analysis and analyze TSV failures electrically to detect failures and their locations in TSV-based 3D IC.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124440094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Tanaka, M. Toyama, Ryo Mori, H. Nakashima, M. Haida, I. Ooshima
{"title":"Early stage chip/package/board co-design techniques for system-on-chip","authors":"M. Tanaka, M. Toyama, Ryo Mori, H. Nakashima, M. Haida, I. Ooshima","doi":"10.1109/EPEPS.2011.6100175","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100175","url":null,"abstract":"With the advancements in semiconductor process technologies in recent years, many circuits are mounted on small dies and the number of interface pins has rapidly increased. The demand for smaller chip/package sizes has come about in order to reduce costs. This paper describes the early stage chip/package/board co-design techniques which reduce chip and package size by cutting down the number of PDN (Power Distribution Network) pads/balls and improve the routability of the package. The key techniques are early stage package/board properties estimation and IR drop estimation. These techniques have a good degree of accuracy even at early stage estimation and a short processing time. From experimental result using a 45-nm process TEG (Test Element Group) chip, the package size was reduced by 21.5%, and the chip size was reduced by 16.4% in comparison with the original design which was designed conventional techniques. The experimental result demonstrates the validation of the proposed techniques.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130411128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yung-Shou Cheng, Hsin-Hung Lu, Michael Chang, Stephen Chang, Bob Liu, R. Wu
{"title":"SI-aware layout and equalizer design to enhance performance of high-speed links in blade servers","authors":"Yung-Shou Cheng, Hsin-Hung Lu, Michael Chang, Stephen Chang, Bob Liu, R. Wu","doi":"10.1109/EPEPS.2011.6100226","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100226","url":null,"abstract":"With increasing demand on higher performance for high speed I/O links, the signal integrity-aware layout schemes and equalization have been attributed as the critical techniques to improve the eye diagram. This paper describes a synthetic design to enhance the system performance and its application to realistic high-speed blade servers. Simulation results are provided to validate the design concept, demonstrating significant improvement in eye height and width by 284% and 96.7%, respectively, for a SATA II link of 1.175m length and 3 Gb/s data rate.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127942400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reduced circuit modeling of mother board and package for a system power delivery analysis","authors":"Jayong Koo, V. Pandit","doi":"10.1109/EPEPS.2011.6100241","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100241","url":null,"abstract":"An algorithm for generating a reduced circuit model of a multi-port power delivery network (PDN) is proposed. Compared to a macromodeling method, this algorithm creates a reduced model which is much simpler and uses only a small portion of CPU time during transient analysis for system power delivery. The algorithm uses an expanded Pi-network to easily visualize the internal branch connection impedances within the PDN. The reduced models efficiently replace the existing macromodels for the motherboard and package in a system analysis where the decoupling capacitors complement the band-limited nature of the reduced model.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134300103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dries Vante Ginste, D. De Zutter, D. Deschrijver, T. Dhaene, F. Canavero
{"title":"Macromodeling based variability analysis of an inverted embedded microstrip line","authors":"Dries Vante Ginste, D. De Zutter, D. Deschrijver, T. Dhaene, F. Canavero","doi":"10.1109/EPEPS.2011.6100213","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100213","url":null,"abstract":"A multivariate macromodel of the per unit length parameters of an inverted embedded microstrip line is built starting from a limited number of highly accurate but computationally expensive electromagnetic simulations. Besides the frequency dependency, the macromodel also encompasses the influence of a geometrical parameter that determines the shape of the cross-section of the metallic interconnect. This allows to assess the influence of the etching process through a variability analysis of the interconnect's behavior in both frequency and time domain. The analysis is carried out via a robust Monte Carlo approach, which has been made computationally feasible thanks to the macromodeling step.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130946516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of a 12Gb/s transceiver for high-density links with discontinuities using modal signaling","authors":"P. Milosevic, J. Schutt-Ainé","doi":"10.1109/EPEPS.2011.6100230","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100230","url":null,"abstract":"In high-speed chip-to-chip single-ended signaling links, far-end crosstalk presents one of the dominant noise sources, limiting the link performance. Diagonalizing the channel using modal decomposition has been proposed to mitigate the crosstalk, but so far only the transceiver designed for uniform low-loss homogenous media channels has been investigated. In this paper, the design of a transceiver system which takes advantage of modal decomposition over a typical memory bus with discontinuities is presented. The proposed approach is verified using circuit-based link simulation.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133643724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High-speed performance of Silicon Bridge die-to-die interconnects","authors":"H. Braunisch, A. Aleksov, S. Lotz, J. Swan","doi":"10.1109/EPEPS.2011.6100196","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100196","url":null,"abstract":"Silicon Bridge is a dense multichip packaging architecture that enables high die-to-die interconnect density and corresponding applications. We describe the basic ideas of the concept, discuss density in the die-to-die interconnect context, and report results of electrical high-speed performance simulations, based on both two-dimensional and three-dimensional electromagnetic modeling.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132184067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Norifumi Sasaoka, Takafumi Ochi, Y. Akiyama, K. Kono, C. Ueda, K. Otsuka
{"title":"Verification of novel technology for power integrity on 16-channel 3Gbps circuit boards","authors":"Norifumi Sasaoka, Takafumi Ochi, Y. Akiyama, K. Kono, C. Ueda, K. Otsuka","doi":"10.1109/EPEPS.2011.6100172","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100172","url":null,"abstract":"Power integrity (PI) for recent electronics circuits and systems is the most important technological issue in the field and has been addressed in important papers through several approaches [1][2]. The latest concept of the best PI condition is recognized as maintaining lower impedance between power and ground lines or planes without any clock frequency dependency, even in the GHz region. We found this concept in a relatively old book [3] from the 1980s; thus, it is not the latest idea. However, it cannot be completely realized by the several previously proposed approaches, including many involving the use of low-inductance capacitances. We are aware that plane power and ground resonance are induced electromagnetic interference(EMI) problems due to resonance caused by eddy currents or multiple reflections of voltage fluctuations. A novel technology was used in our previous study only using a conductive layer of dispersed metal particles [4]. The structure is consisted of a conventional FR-4 printed circuit board in which the copper ground plane was replaced with a metal particle conductive layer [4]. This structure improved the PI for any clock frequency especially in GHz region with an impedance of less than 1 Ω. This improvement is verified by an actual 16-channel 3 Gbps/pin I/O interface board in this study. Even though the simultaneous switching of two sets of 16 drivers gave a fairly high current slew-rate of (8 mA × 32) / 60 ps = 4.27 × 109 A/s, the PI status can be verified by the condition. Result was that PIS structure kept better than Cu plane in the VDD fluctuation.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123902068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Alternative SPICE implementation of circuit uncertainties based on orthogonal polynomials","authors":"P. Manfredi, I. Stievano, F. Canavero","doi":"10.1109/EPEPS.2011.6100181","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100181","url":null,"abstract":"The impact on circuit performance of parameters uncertainties due to possible tolerances or partial information on devices can be effectively evaluated by describing the resulting stochastic problem in terms of orthogonal polynomial expansions of electrical parameters and of circuit voltages and currents. This contribution formalizes a rule for the construction of an augmented instance of the original circuit, that provides a systematic solution approach for the unknown coefficients of the expanded electrical variables. The use of SPICE as a solution engine of the augmented circuit is straightforward, thus providing a convenient and efficient alternative to the conventional approach SPICE uses for uncertainty analysis. An application example involving the stochastic simulation of a digital link with variable substrate parameters demonstrates the potential of the proposed approach.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124080030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Capacitance calculation for a shared-antipad via structure using an integral equation method based on partial capacitance","authors":"Hanfeng Wang, A. Ruehli, J. Fan","doi":"10.1109/EPEPS.2011.6100244","DOIUrl":"https://doi.org/10.1109/EPEPS.2011.6100244","url":null,"abstract":"An integral equation method used for capacitance extraction for axially symmetric geometries is extended in this paper to calculate the via-plane capacitances in shared-antipad via structures, by changing the circular ring cells to arc ones. The proposed method is validated with a commercial finite element method based tool for a typical structure used in modern high-speed printed circuit design.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129470045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}