Verification of novel technology for power integrity on 16-channel 3Gbps circuit boards

Abstract

Power integrity (PI) for recent electronics circuits and systems is the most important technological issue in the field and has been addressed in important papers through several approaches [1][2]. The latest concept of the best PI condition is recognized as maintaining lower impedance between power and ground lines or planes without any clock frequency dependency, even in the GHz region. We found this concept in a relatively old book [3] from the 1980s; thus, it is not the latest idea. However, it cannot be completely realized by the several previously proposed approaches, including many involving the use of low-inductance capacitances. We are aware that plane power and ground resonance are induced electromagnetic interference(EMI) problems due to resonance caused by eddy currents or multiple reflections of voltage fluctuations. A novel technology was used in our previous study only using a conductive layer of dispersed metal particles [4]. The structure is consisted of a conventional FR-4 printed circuit board in which the copper ground plane was replaced with a metal particle conductive layer [4]. This structure improved the PI for any clock frequency especially in GHz region with an impedance of less than 1 Ω. This improvement is verified by an actual 16-channel 3 Gbps/pin I/O interface board in this study. Even though the simultaneous switching of two sets of 16 drivers gave a fairly high current slew-rate of (8 mA × 32) / 60 ps = 4.27 × 109 A/s, the PI status can be verified by the condition. Result was that PIS structure kept better than Cu plane in the VDD fluctuation.