2012 IEEE 30th International Conference on Computer Design (ICCD)最新文献_第9页

RFiop: RF-memory path to address on-package I/O pad and memory controller scalability RFiop:射频存储器路径，用于解决包上I/O垫和存储器控制器的可扩展性

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378638

M. Marino

{"title":"RFiop: RF-memory path to address on-package I/O pad and memory controller scalability","authors":"M. Marino","doi":"10.1109/ICCD.2012.6378638","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378638","url":null,"abstract":"Off-chip memory parallelism can be improved by having multiple memory controllers (MCs). However, MCs scalability is limited by the number and area of I/O pads/pins allocated to them, besides power. In order to address the scalability of MCs and I/O pads in a multi-chip (MCP) flip-chip package, we propose RFiop - a scalable memory organization based on wired-RF, which replaces the traditional MC-DRAM, mostly composed by MC, and I/O pad/pin related structures with RF-designed RFMCs - MCs coupled to RF transmitters (TX) / receivers (RX), RF coplanar waveguides (CPW) - defined as RFpads, and off-die ranks placed on a coplanar fashion. RFiop explores the on-package area to fit off-die ranks, which are connected to the RFMCs via CPWs. Configuring RFiop with off-die lower data-rate-DDR3 ranks, RFiop scales bandwidth for 16 out-of-order (OOO) cores, using 16 RFMCs with about 4 RFpads per RFMC. RFiop leverages performance and bandwidth by a factor of up to 3.95×, while reducing latency in up to 47%, assuming an electrical-based solution under I/O pad constraints as baseline. Dedicating the baseline area to placing several RFMCs, RFiop improves bandwidth in up to 2.68×.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130645971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

A high-performance, low-overhead microarchitecture for secure program execution 用于安全程序执行的高性能、低开销的微体系结构

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378624

A. Kanuparthi, R. Karri, Gaston Ormazabal, Sateesh Addepalli

{"title":"A high-performance, low-overhead microarchitecture for secure program execution","authors":"A. Kanuparthi, R. Karri, Gaston Ormazabal, Sateesh Addepalli","doi":"10.1109/ICCD.2012.6378624","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378624","url":null,"abstract":"High performance and low power consumption have traditionally been the primary design goals for computer architects. With computer systems facing a wave of attacks that disrupt their normal execution or leak sensitive data, computer security is no longer an afterthought. Dynamic integrity checking has emerged as a possible solution to protect computer systems by thwarting various attacks. Dynamic integrity checking involves calculation of hashes of the instructions in the code being executed and comparing these hashes against corresponding precomputed hashes at runtime. The processor pipeline is stalled and the instructions are not allowed to commit until the integrity check is complete. Such an approach has severe performance implications as it stalls the pipeline for several cycles. In this paper, we propose a hardware-based dynamic integrity checking approach that does not stall the processor pipeline. We permit the instructions to commit before the integrity check is complete, and allow them to make changes to the register file, but not the data cache. The system is rolled back to a known state if the checker deems the instructions as modified. Our experiments show an average performance overhead of 1.66%, area overhead of 4.25%, and a power overhead of 2.45% over a baseline processor.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131297297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Providing cost-effective on-chip network bandwidth in GPGPUs 在gpgpu中提供高性价比的片上网络带宽

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378671

H. Kim, John Kim, Woong Seo, Yeon-Gon Cho, Soojung Ryu

引用次数: 35

A case for small row buffers in non-volatile main memories 非易失性主存储器中小行缓冲区的一种情况

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378685

Justin Meza, Jing Li, O. Mutlu

{"title":"A case for small row buffers in non-volatile main memories","authors":"Justin Meza, Jing Li, O. Mutlu","doi":"10.1109/ICCD.2012.6378685","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378685","url":null,"abstract":"DRAM-based main memories have read operations that destroy the read data, and as a result, must buffer large amounts of data on each array access to keep chip costs low. Unfortunately, system-level trends such as increased memory contention in multi-core architectures and data mapping schemes that improve memory parallelism lead to only a small amount of the buffered data to be accessed. This makes buffering large amounts of data on every memory array access energy-inefficient; yet organizing DRAM chips to buffer small amounts of data is costly, as others have shown [11]. Emerging non-volatile memories (NVMs) such as PCM, STT-RAM, and RRAM, however, do not have destructive read operations, opening up opportunities for employing small row buffers without incurring additional area penalty and/or design complexity. In this work, we discuss and evaluate architectural changes to enable small row buffers at a low cost in NVMs. We find that on a multi-core system, reducing the row buffer size can greatly reduce main memory dynamic energy compared to a DRAM baseline with large row sizes, without greatly affecting endurance, and for some NVM technologies, leads to improved performance.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121250148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 58

Architectural simulations of a fast, source-synchronous ring-based Network-on-Chip design 基于环的快速源同步片上网络设计的体系结构仿真

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378684

Ayan Mandal, S. Khatri, R. Mahapatra

引用次数: 3

Clock mesh synthesis method using the Earth Mover's Distance under transformations 利用地球移动距离变换的时钟网格合成方法

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378627

Y. Teng, B. Taskin

引用次数: 4

The performance of hypermesh NoCs in FPGAs fpga中超网状noc的性能

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378689

Mohammadreza Binesh Marvasti, T. Szymanski

引用次数: 8

Adaptive memory architecture for real-time image warping 实时图像变形的自适应存储器结构

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378680

Andy Motten, L. Claesen, Yun Pan

引用次数: 9

Efficient verification of out-of-order behaviors with relaxed scoreboards 通过轻松的记分板有效地验证无序行为

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378698

Leandro S. Freitas, Gabriel A. G. Andrade, L. Santos

引用次数: 0

Exploiting multi-level scratchpad memories for time-predictable multicore computing 为时间可预测的多核计算开发多级刮刮板存储器

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378618

Yu Liu, Wei Zhang

引用次数: 9