2012 IEEE 30th International Conference on Computer Design (ICCD)最新文献_第10页

Maximizing crosstalk-induced slowdown during path delay test 在路径延迟测试中最大化串扰引起的减速

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378635

Dibakar Gope, D. Walker

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引用次数: 8

A high-performance, low-overhead microarchitecture for secure program execution 用于安全程序执行的高性能、低开销的微体系结构

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378624

A. Kanuparthi, R. Karri, Gaston Ormazabal, Sateesh Addepalli

{"title":"A high-performance, low-overhead microarchitecture for secure program execution","authors":"A. Kanuparthi, R. Karri, Gaston Ormazabal, Sateesh Addepalli","doi":"10.1109/ICCD.2012.6378624","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378624","url":null,"abstract":"High performance and low power consumption have traditionally been the primary design goals for computer architects. With computer systems facing a wave of attacks that disrupt their normal execution or leak sensitive data, computer security is no longer an afterthought. Dynamic integrity checking has emerged as a possible solution to protect computer systems by thwarting various attacks. Dynamic integrity checking involves calculation of hashes of the instructions in the code being executed and comparing these hashes against corresponding precomputed hashes at runtime. The processor pipeline is stalled and the instructions are not allowed to commit until the integrity check is complete. Such an approach has severe performance implications as it stalls the pipeline for several cycles. In this paper, we propose a hardware-based dynamic integrity checking approach that does not stall the processor pipeline. We permit the instructions to commit before the integrity check is complete, and allow them to make changes to the register file, but not the data cache. The system is rolled back to a known state if the checker deems the instructions as modified. Our experiments show an average performance overhead of 1.66%, area overhead of 4.25%, and a power overhead of 2.45% over a baseline processor.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131297297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Providing cost-effective on-chip network bandwidth in GPGPUs 在gpgpu中提供高性价比的片上网络带宽

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378671

H. Kim, John Kim, Woong Seo, Yeon-Gon Cho, Soojung Ryu

引用次数: 35

Ring oscillator physical unclonable function with multi level supply voltages 环形振荡器具有多电平供电电压的物理不可克隆功能

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-07-17 DOI: 10.1109/ICCD.2012.6378703

S. Mansouri, E. Dubrova

引用次数: 50

Xpipes: A latency insensitive parameterized network-on-chip architecture for multi-processor SoCs Xpipes:用于多处理器soc的延迟不敏感参数化片上网络架构

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2003-10-13 DOI: 10.1109/ICCD.2012.6378615

M. Dall'Osso, G. Biccari, L. Giovannini, D. Bertozzi, L. Benini

引用次数: 94

Exploiting microarchitectural redundancy for defect tolerance 利用微架构冗余来容忍缺陷

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2003-10-13 DOI: 10.1109/ICCD.2012.6378613

P. Shivakumar, S. Keckler, C. R. Moore, D. Burger

{"title":"Exploiting microarchitectural redundancy for defect tolerance","authors":"P. Shivakumar, S. Keckler, C. R. Moore, D. Burger","doi":"10.1109/ICCD.2012.6378613","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378613","url":null,"abstract":"The continued increase in microprocessor clock frequency that has come from advancements in fabrication technology and reductions in feature size, creates challenges in maintaining both manufacturing yield rates and long-term reliability of devices. Methods based on defect detection and reduction may not offer a scalable solution due to cost of eliminating contaminants in the manufacturing process and increasing chip complexity. This paper proposes to use the inherent redundancy available in existing and future chip microarchitectures to improve yield and enable graceful performance degradation in fail-in-place systems. We introduce a new yield metric called performance averaged yield (Ypav) which accounts both for fully functional chips and those that exhibit some performance degradation. Our results indicate that at 250nm we are able to increase the Ypav of a uniprocessor with only redundant rows in its caches from a base value of 85% to 98% using microarchitectural redundancy. Given constant chip area, shrinking feature sizes increases fault susceptibility and reduces the base Ypav to 60% at 50nm, which exploiting microarchitectural redundancy then increases to 99.6%.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129320264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 85

Power-sensitive multithreaded architecture 对功率敏感的多线程架构

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2012.6378610

J. Seng, D. Tullsen, George Z. N. Cai

引用次数: 15

FlexRAM: Toward an advanced Intelligent Memory system FlexRAM:迈向先进的智能存储系统

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 1999-10-10 DOI: 10.1109/ICCD.2012.6378608

Y. Kang, Wei Huang, Seung-Moon Yoo, D. Franklin, Zhenzhou Ge, V. Lam, P. Pattnaik, J. Torrellas

引用次数: 160