2012 IEEE 30th International Conference on Computer Design (ICCD)最新文献_第10页

Improving inclusive cache performance with two-level eviction priority 通过两级退出优先级提高包容性缓存性能

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378668

Lingda Li, Dong Tong, Zichao Xie, Junlin Lu, Xu Cheng

{"title":"Improving inclusive cache performance with two-level eviction priority","authors":"Lingda Li, Dong Tong, Zichao Xie, Junlin Lu, Xu Cheng","doi":"10.1109/ICCD.2012.6378668","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378668","url":null,"abstract":"Inclusive cache hierarchies are widely adopted in modern processors, since they can simplify the implementation of cache coherence. However, it sacrifices some performance to guarantee inclusion. Many recent intelligent management policies are proposed to improve the last-level cache (LLC) performance by evicting blocks with poor locality earlier. Unfortunately, they are inapplicable in inclusive LLCs. In this paper, we propose Two-level Eviction Priority (TEP) policy. Besides the eviction priority provided by the baseline replacement policy, TEP appends an additional high level of eviction priority to LLC blocks, which is decided at the insertion time and cannot be changed during their lifetime in the LLC. When blocks with high eviction priority are not in inner caches anymore, they get evicted from the LLC preferentially. Thus, the LLC can retain more useful blocks to improve performance. TEP can cooperate well with various baseline replacement policies. Our evaluation shows that TEP with NRU can improve the performance of inclusive LLCs significantly while requiring negligible extra storage. It also outperforms other recent proposals including QBS, DIP, and DRRIP.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116637529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Locating faults in application-dependent interconnects of SRAM based FPGAs 基于SRAM的fpga应用相关互连故障定位

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378678

T. N. Kumar, H. Almurib, F. Lombardi

引用次数: 3

Maximizing crosstalk-induced slowdown during path delay test 在路径延迟测试中最大化串扰引起的减速

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378635

Dibakar Gope, D. Walker

{"title":"Maximizing crosstalk-induced slowdown during path delay test","authors":"Dibakar Gope, D. Walker","doi":"10.1109/ICCD.2012.6378635","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378635","url":null,"abstract":"In this paper, we present a timing-driven test generator to sensitize multiple aligned aggressors coupled to a delay-sensitive victim path to detect the combination of a delay spot defect and crosstalk-induced slowdown. The framework uses parasitic capacitance information, timing windows and crosstalk-induced delay estimates to screen out unaligned or ineffective aggressors coupled to a victim path, speeding up crosstalk pattern generation. In order to induce maximum crosstalk slowdown along a path, aggressors are prioritized based on their potential delay increase and timing alignment. The test generation engine introduces the concept of alignment-driven path sensitization to generate paths from inputs to coupled aggressor nets that meet timing alignment and direction requirements. In addition, two new crosstalk-driven dynamic test compaction algorithms are developed to control the increase in test pattern count. The proposed test generation algorithm is applied to ISCAS85 and ISCAS89 benchmark circuits. SPICE simulation results demonstrate the ability of the alignment-driven test generator to increase crosstalk-induced delays along victim paths.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133109242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Ring oscillator physical unclonable function with multi level supply voltages 环形振荡器具有多电平供电电压的物理不可克隆功能

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-07-17 DOI: 10.1109/ICCD.2012.6378703

S. Mansouri, E. Dubrova

引用次数: 50

Xpipes: A latency insensitive parameterized network-on-chip architecture for multi-processor SoCs Xpipes:用于多处理器soc的延迟不敏感参数化片上网络架构

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2003-10-13 DOI: 10.1109/ICCD.2012.6378615

M. Dall'Osso, G. Biccari, L. Giovannini, D. Bertozzi, L. Benini

引用次数: 94

Exploiting microarchitectural redundancy for defect tolerance 利用微架构冗余来容忍缺陷

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2003-10-13 DOI: 10.1109/ICCD.2012.6378613

P. Shivakumar, S. Keckler, C. R. Moore, D. Burger

{"title":"Exploiting microarchitectural redundancy for defect tolerance","authors":"P. Shivakumar, S. Keckler, C. R. Moore, D. Burger","doi":"10.1109/ICCD.2012.6378613","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378613","url":null,"abstract":"The continued increase in microprocessor clock frequency that has come from advancements in fabrication technology and reductions in feature size, creates challenges in maintaining both manufacturing yield rates and long-term reliability of devices. Methods based on defect detection and reduction may not offer a scalable solution due to cost of eliminating contaminants in the manufacturing process and increasing chip complexity. This paper proposes to use the inherent redundancy available in existing and future chip microarchitectures to improve yield and enable graceful performance degradation in fail-in-place systems. We introduce a new yield metric called performance averaged yield (Ypav) which accounts both for fully functional chips and those that exhibit some performance degradation. Our results indicate that at 250nm we are able to increase the Ypav of a uniprocessor with only redundant rows in its caches from a base value of 85% to 98% using microarchitectural redundancy. Given constant chip area, shrinking feature sizes increases fault susceptibility and reduces the base Ypav to 60% at 50nm, which exploiting microarchitectural redundancy then increases to 99.6%.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129320264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 85

Power-sensitive multithreaded architecture 对功率敏感的多线程架构

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2012.6378610

J. Seng, D. Tullsen, George Z. N. Cai

引用次数: 15

FlexRAM: Toward an advanced Intelligent Memory system FlexRAM:迈向先进的智能存储系统

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 1999-10-10 DOI: 10.1109/ICCD.2012.6378608

Y. Kang, Wei Huang, Seung-Moon Yoo, D. Franklin, Zhenzhou Ge, V. Lam, P. Pattnaik, J. Torrellas

引用次数: 160