2012 IEEE 30th International Conference on Computer Design (ICCD)最新文献

Oblivious routing design for mesh networks to achieve a new worst-case throughput bound 网状网络的遗忘路由设计，以实现新的最坏情况吞吐量边界

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-12-13 DOI: 10.1109/ICCD.2012.6378674

Guang Sun, Chia-Wei Chang, Bill Lin, Lieguang Zeng

{"title":"Oblivious routing design for mesh networks to achieve a new worst-case throughput bound","authors":"Guang Sun, Chia-Wei Chang, Bill Lin, Lieguang Zeng","doi":"10.1109/ICCD.2012.6378674","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378674","url":null,"abstract":"1/2 network capacity is often believed to be the limit of worst-case throughput for mesh networks. However, this paper provides a new worst-case throughput bound, which is higher than 1/2 network capacity, for odd radix two-dimensional mesh networks. In addition, we propose a routing algorithm called U2TURN that can achieve this worst-case throughput bound for odd radix meshes. For even radix meshes, we prove that U2TURN achieves the optimal worst-case throughput, namely, half of network capacity. U2TURN considers all routing paths with at most 2 turns and distributes the traffic loads uniformly in both X and Y dimensions. Theoretical analysis and simulation results show that U2TURN outperforms existing routing algorithms in worst-case throughput. Moreover, U2TURN achieves good average-throughput at the expense of approximately 1.5× minimal average hop count. For asymmetric meshes, we further propose an algorithm called “U2TURN-A” and provide theoretical analysis for different algorithms. Both theoretical analysis and simulation show that U2TURN and U2TURN-A outperform existing algorithms VAL, DOR and O1TURN in both worst-case and average throughput for asymmetric meshes.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131500847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Modeling economics of LSI design and manufacturing for test design selection 为测试设计选择进行大规模集成电路设计和制造的经济建模

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378701

H. Ichihara, N. Shimizu, T. Iwagaki, Tomoo Inoue

引用次数: 0

DuSCA: A multi-channeling strategy for doubling communication capacity in wireless NoC DuSCA:无线NoC中通信容量加倍的多信道策略

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378620

Yi Wang, Dan Zhao, Jian Li

引用次数: 3

A comparative study of wearout mechanisms in state-of-art microprocessors 最新微处理器耗损机制的比较研究

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378651

Chang-Chih Chen, Fahad Ahmed, L. Milor

引用次数: 11

Adaptable intrusion detection using partial runtime reconfiguration 使用部分运行时重新配置的适应性入侵检测

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378633

M. Rahmatian, H. Kooti, I. Harris, E. Bozorgzadeh

引用次数: 1

ECC string: Flexible ECC management for low-cost error protection of L2 caches ECC字符串:灵活的ECC管理，用于L2缓存的低成本错误保护

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378699

Jeongkyu Hong, Soontae Kim

引用次数: 1

A retrospective look at xpipes: The exciting ride from a design experience to a design platform for nanoscale networks-on-chip 回顾xpipes:从设计体验到纳米级片上网络设计平台的激动人心的历程

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378614

D. Bertozzi, L. Benini

引用次数: 1

Exposing vulnerabilities of untrusted computing platforms 暴露不可信计算平台的漏洞

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378629

Yier Jin, M. Maniatakos, Y. Makris

引用次数: 26

Designing pipelined delay lines with dynamically-adaptive granularity for low-energy applications 低能耗应用中动态自适应粒度的流水线延迟线设计

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378660

Christos Vezyrtzis, Y. Tsividis, S. Nowick

{"title":"Designing pipelined delay lines with dynamically-adaptive granularity for low-energy applications","authors":"Christos Vezyrtzis, Y. Tsividis, S. Nowick","doi":"10.1109/ICCD.2012.6378660","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378660","url":null,"abstract":"A calibrated delay line is a key component in many modern digital systems. Traditionally, these lines are designed as real-time pipelines with static granularity, fine enough to handle a worst-case input rate. However, due to their rigid structure, they have sub-optimal energy for low- and varying-rate input streams. We introduce a complete methodology for designing reconfigurable delay lines which dynamically adapt granularity to traffic, on-the-fly, without stalling or disturbing normal operation. These lines have two modes: coarse- and fine-grain. During sparser traffic, the system is reconfigured to coarse-grain mode, thereby reducing total energy, and it reverts to fine-grain mode during denser traffic. In each case, overall delay is preserved. This strategy is especially beneficial for applications where input traffic is highly varied. The particular focus of this paper is on one promising domain, continuous-time digital signal processors (CT DSP's), a new class of processors targeting low-energy applications. The proposed system includes two lightweight asynchronous control blocks: a digital controller to continuously monitor input traffic, and a micropipeline to dynamically reconfigure the entire delay line. With a complete implementation in a 0.13 um IBM CMOS technology, post-layout simulations demonstrate an average overall dynamic power reduction up to 45.5% compared to a non-adaptive design, with only minimal area overhead. The design methodology is modular, supporting extensions to multiple configuration modes to provide even greater power reduction for a variety of input traffic. While results are presented for CT DSP's, significant benefits are also expected in many other domains where delay lines are used.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130051721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Fast development of hardware-based run-time monitors through architecture framework and high-level synthesis 通过架构框架和高级综合快速开发基于硬件的运行时监视器

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378669

Mohamed Ismail, G. Suh

{"title":"Fast development of hardware-based run-time monitors through architecture framework and high-level synthesis","authors":"Mohamed Ismail, G. Suh","doi":"10.1109/ICCD.2012.6378669","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378669","url":null,"abstract":"Recent work has shown that hardware-based runtime monitoring techniques can significantly enhance security and reliability of computing systems with minimal performance and energy overheads. However, the cost and time for implementing such a hardware-based mechanism presents a major challenge in deploying the run-time monitoring techniques in real systems. This paper addresses this design complexity problem through a common architecture framework and high-level synthesis. Similar to customizable processors such as Tensilica Xtensa where designers only need to write a small piece of code that describes a custom instruction, our framework enables designers to only specify monitoring operations. The framework provides common functions such as collecting a trace of execution, maintaining meta-data, and interfacing with software. To further reduce the design complexity, we also explore using a high-level synthesis tool (Cadence C-to-Silicon) so that hardware monitors can be described in a high-level language (SystemC) instead of in RTL such as Verilog and VHDL. To evaluate our approach, we implemented a set of monitors including soft-error checking, uninitialized memory checking, dynamic information flow tracking, and array boundary checking in our framework. Our results suggest that our monitor framework can greatly reduce the amount of code that needs to be specified for each extension and the high-level synthesis can achieve comparable area, performance, and power consumption to handwritten RTL.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130998944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3