2012 IEEE 30th International Conference on Computer Design (ICCD)最新文献_第2页

Aurora: A thermally resilient photonic network-on-chip architecture Aurora:一种热弹性光子网络芯片架构

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378667

Amer Qouneh, Zhongqi Li, Madhura Joshi, Wangyuan Zhang, Xin Fu, Tao Li

{"title":"Aurora: A thermally resilient photonic network-on-chip architecture","authors":"Amer Qouneh, Zhongqi Li, Madhura Joshi, Wangyuan Zhang, Xin Fu, Tao Li","doi":"10.1109/ICCD.2012.6378667","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378667","url":null,"abstract":"With silicon optical technology moving towards maturity, the use of photonic network-on-chip (NoCs) for global chip communication is emerging as a promising solution to communication requirements of future many core processors. It is expected that photonic NoCs will play an important role in alleviating current power, latency, and bandwidth constraints. However, photonic NoCs are sensitive to ambient temperature variations because their basic constituents, ring resonators, are themselves sensitive to those variations. Since ring resonators are basic building blocks for photonic modulators, switches, multiplexers, and demultiplexers, variations of on-chip temperature pose serious challenges to the proper operation of photonic NoCs. Proposed methods that mitigate the effects of temperature at device level are either difficult to use in CMOS processes or not suitable for large scale implementation. In this paper, we propose Aurora, a thermally resilient photonic NoC architecture design that supports reliable and low bit error rate (BER) on-chip communications in the presence of large temperature variations. Our proposed architecture leverages solutions at both device and architecture layers that synergistically provide significant improvements. To compensate for small temperature variations, our design varies the bias current through ring resonators. For larger temperature variations, we propose architecture-level techniques to re-route messages away from hot regions, and through cooler regions, to their destinations, thereby lowering BER. Our simulation results show that Aurora provides a robust architectural solution to handle temperature variation effects on future photonic NoCs. For instance, average BER and message error rate (MER) are reduced by 78% and 30% respectively when the combined device and architectural technique (SPF) is applied. From the perspective of power efficiency, Aurora is also superior to conventional photonic NoC architectures by as much as 33%.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129171697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Fast error aware model for arithmetic and logic circuits 用于算术和逻辑电路的快速错误感知模型

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378659

Samy Zaynoun, Muhammed S. Khairy, A. Eltawil, F. Kurdahi, A. Djahromi

引用次数: 20

Engineering crossbar based emerging memory technologies 基于工程交叉杆的新兴存储技术

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378682

Sachhidh Kannan, Jeyavijayan Rajendran, R. Karri, O. Sinanoglu

引用次数: 2

3D-NoC: Reconfigurable 3D photonic on-chip interconnect for multicores 3D- noc:用于多核的可重构3D光子片上互连

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378672

R. Morris, Avinash Karanth Kodi, A. Louri

{"title":"3D-NoC: Reconfigurable 3D photonic on-chip interconnect for multicores","authors":"R. Morris, Avinash Karanth Kodi, A. Louri","doi":"10.1109/ICCD.2012.6378672","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378672","url":null,"abstract":"The power dissipation of metallic interconnects in future multicore architectures is projected to be a major bottleneck as we scale to sub-nanometer regime. This has motivated researchers to develop alternate power-efficient technology solutions to the performance limitations of future multicores. Nanophotonic interconnects (NIs) is a disruptive technology solution that is capable of delivering the communication bandwidth at low power dissipation when the number of cores is scaled to large numbers. Similarly, 3D stacking is another interconnect technology solution that can lead to low energy/bit for communication. In this paper, we propose to combine NIs with with 3D stacking to develop a scalable, reconfigurable, power-efficient and high-performance interconnect for future many-core systems called 3D-NoC. We propose to develop a multi-layer NIs that can dynamically reconfigure without system intervention and allocate channel bandwidth from less utilized links to more utilized communication links. Our simulation results indicate that the performance can be further improved by 10%-25% for Splash-2, PARSEC and SPEC CPU2006 benchmarks.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114988712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

A physical unclonable function based on setup time violation 基于设置时间冲突的物理不可克隆函数

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378630

D. Hély, Maurin Augagneur, Y. Clauzel, Jeremy Dubeuf

引用次数: 1

Automatic assertion extraction in gate-level simulation using GPGPUs 基于gpgpu的门级仿真中的自动断言提取

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378704

Shohei Ono, Takeshi Matsumoto, M. Fujita

引用次数: 0

Parameterized free space redistribution for engineering change in placement of integrated circuits 工程中集成电路布局变化的参数化自由空间再分配

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378670

Taraneh Taghavi, Shyam Ramji, F. Musante, Suhasini Rege

{"title":"Parameterized free space redistribution for engineering change in placement of integrated circuits","authors":"Taraneh Taghavi, Shyam Ramji, F. Musante, Suhasini Rege","doi":"10.1109/ICCD.2012.6378670","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378670","url":null,"abstract":"In this paper we present a method for parameterized free space redistribution of a fragmented placement. The fragmentation problem arises in different contexts within the physical design automation, including post physical synthesis for filler cell insertion, incremental placement, timing optimization, and late mode ECO fix-ups. To address this problem, we apply a post-placement parameterized method of defragmentation. This method involves capturing a view of a given placement and modeling a dynamic programming problem to optimally maximize the amount of so-called useful free space as defined by a given set of parameters. The parameters act as constraints to preserve the row placement and order of the cells while minimizing the perturbation of the whole design for a successful timing and design closure. Experimental results demonstrate that by applying the proposed technique, on average, 9.7% increase in the number of inserted filler cells and 5.7% improvement in the success rate of incremental placement requests can be achieved with minimal or no impact on timing and wirelength. Moreover, when deployed in early mode buffering for timing optimization, this technique can result in 3% reduction in the number of paths with negative slacks.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122118962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hierarchical modeling of Phase Change memory for reliable design 面向可靠性设计的相变存储器分层建模

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378626

Zihan Xu, K. Sutaria, Chengen Yang, C. Chakrabarti, Yu Cao

引用次数: 18

HPRA: A pro-active Hotspot-Preventive high-performance routing algorithm for Networks-on-Chips HPRA:一种面向片上网络的主动热点预防高性能路由算法

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378648

E. Kakoulli, V. Soteriou, T. Theocharides

{"title":"HPRA: A pro-active Hotspot-Preventive high-performance routing algorithm for Networks-on-Chips","authors":"E. Kakoulli, V. Soteriou, T. Theocharides","doi":"10.1109/ICCD.2012.6378648","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378648","url":null,"abstract":"The inherent spatio-temporal unevenness of traffic flows in Networks-on-Chips (NoCs) can cause unforeseen, and in cases, severe forms of congestion, known as hotspots. Hotspots reduce the NoC's effective throughput, where in the worst case scenario, the entire network can be brought to an unrecoverable halt as a hotspot(s) spreads across the topology. To alleviate this problematic phenomenon several adaptive routing algorithms employ online load-balancing functions, aiming to reduce the possibility of hotspots arising. Most, however, work passively, merely distributing traffic as evenly as possible among alternative network paths, and they cannot guarantee the absence of network congestion as their reactive capability in reducing hotspot formation(s) is limited. In this paper we present a new pro-active Hotspot-Preventive Routing Algorithm (HPRA) which uses the advance knowledge gained from network-embedded Artificial Neural Network-based (ANN) hotspot predictors to guide packet routing across the network in an effort to mitigate any unforeseen near-future occurrences of hotspots. These ANNs are trained offline and during multicore operation they gather online buffer utilization data to predict about-to-be-formed hotspots, promptly informing the HPRA routing algorithm to take appropriate action in preventing hotspot formation(s). Evaluation results across two synthetic traffic patterns, and traffic benchmarks gathered from a chip multiprocessor architecture, show that HPRA can reduce network latency and improve network throughput up to 81% when compared against several existing state-of-the-art congestion-aware routing functions. Hardware synthesis results demonstrate the efficacy of the HPRA mechanism.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127224435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Energy modelling of embedded multimedia streaming applications with GStreamer on heterogeneous MPSoC 基于GStreamer的异构MPSoC嵌入式多媒体流应用的能量建模

2012 IEEE 30th International Conference on Computer Design (ICCD) Pub Date : 2012-09-30 DOI: 10.1109/ICCD.2012.6378686

Mickael Lanoe, E. Senn

引用次数: 1