Automatic assertion extraction in gate-level simulation using GPGPUs

Abstract

In modern VLSI designs, assertions play an important role to understand design intention and ensure correctness of designs. In this paper, we consider to generate assertions from simulation results. This assertion extraction is performed by examining whether a logical relation is satisfied among a set of signals. We propose to accelerate it by utilizing a highly parallelized computation performed by GPGPUs. Through the experiments with designs from industry, our implementation on GPGPU runs 30 times faster than a software implementation.