Locating faults in application-dependent interconnects of SRAM based FPGAs

This paper presents a new method for locating multiple faults in an interconnect following application testing of an FPGA. This method utilizes conditions related to the interconnect structure and in particular, the presence of paths of nets that are either disjoint or joint between the primary input and at least one primary output. They yield to a rather adaptive approach by which faults are hierarchically located using the walking-1 test set. The proposed method is not dependent on net ordering and is capable to locate multiple stuck-at and pairwise bridging faults. This process requires 1+log2 k test configurations for multiple stuck-at location and 2+2log2 k additional test configurations to locate more than one pair-wise bridging faults (where k denotes the maximum combinational depth). As validated by simulation for benchmark circuits (implemented on the Xilinx Virtex4), the proposed method results in a significant reduction in the number of configurations.