2016 74th Annual Device Research Conference (DRC)最新文献

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Low-noise high-gain tunneling staircase photodetector 低噪声高增益隧道楼梯光电探测器
2016 74th Annual Device Research Conference (DRC) Pub Date : 2016-06-19 DOI: 10.1109/DRC.2016.7548480
S. Maddox, M. Ren, A. Rockwell, Yaojia Chen, M. Woodson, J. Campbell, S. Bank
{"title":"Low-noise high-gain tunneling staircase photodetector","authors":"S. Maddox, M. Ren, A. Rockwell, Yaojia Chen, M. Woodson, J. Campbell, S. Bank","doi":"10.1109/DRC.2016.7548480","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548480","url":null,"abstract":"Avalanche photodiodes (APD) are important components in short-wave and mid-wave infrared detection systems (imaging, laser radar, communications, etc.) because their internal gain can improve receiver sensitivity and enable the detection of weak photon fluxes. However, gain originates from impact ionization, a stochastic process that results in excess noise and limits the gain-bandwidth product. The staircase APD was proposed as the solid-state analog of the photomultiplier tube where impact ionization events occur proximate to the sharp bandgap discontinuity of each step. As a result, the gain process is more deterministic, with concomitant reduction in gain fluctuations and, thus, lower excess noise. An additional advantage of the staircase structure is that the kinetic energy change required to initiate impact ionization events is supplied by band engineering and a modest applied field, rather than large bias, which is typically 10's of Volts for conventional APDs. Unfortunately, initial studies of staircase APDs used the AlxGai_xAs material system, which has inadequate band offsets and the projected noise characteristics were never achieved, We recently demonstrated the first staircase APDs, where a single step exhibits a constant gain of ~2x over a range of bias, temperature, and excitation wavelength, enabled by the digital alloy growth of high-quality AlInAsSb, lattice-matched to GaSb across the full range of direct bandgap compositions.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129813348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Creating wide band gap LEDs without P-doping 制造无p掺杂的宽带隙led
2016 74th Annual Device Research Conference (DRC) Pub Date : 2016-06-19 DOI: 10.1109/DRC.2016.7548479
S. Agarwal, J. Dickerson, J. Tsao
{"title":"Creating wide band gap LEDs without P-doping","authors":"S. Agarwal, J. Dickerson, J. Tsao","doi":"10.1109/DRC.2016.7548479","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548479","url":null,"abstract":"Wide band gap semiconductors like AlN typically cannot be efficiently p-doped: acceptor levels are far from the valence band-edge, preventing holes from activating. This means that pn-junctions cannot be created, and the semiconductor is less useful, a particular problem for deep Ultraviolet (UV) optoelectronics.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128428642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Electrochemical micro-electrode arrays for measurement of transient concentration gradients of hydrogen peroxide 测量过氧化氢瞬态浓度梯度的电化学微电极阵列
2016 74th Annual Device Research Conference (DRC) Pub Date : 2016-06-19 DOI: 10.1109/DRC.2016.7548459
Siddarth V. Sridharan, J. F. Rivera, Xin Jin, D. Janes, J. Rickus, M. Alam
{"title":"Electrochemical micro-electrode arrays for measurement of transient concentration gradients of hydrogen peroxide","authors":"Siddarth V. Sridharan, J. F. Rivera, Xin Jin, D. Janes, J. Rickus, M. Alam","doi":"10.1109/DRC.2016.7548459","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548459","url":null,"abstract":"Understanding biological processes such as neurotransmitter release and reuptake in neurons, glucose transport for adapted cell metabolism in cancer cells involves measuring dynamic concentration gradients with diffusion time constants varying from a few hundred milliseconds to a few minutes. [1] Many prior electrochemical sensor reports utilize single electrodes, and achieve spatial information using techniques such as the self-referencing approach, which employs a moving probe. These approaches suffer from setup complexity, poor temporal and spatial resolution and poor suitability for portable, multi-analyte, high throughput applications. [2] In this work, an array of individually addressable platinum micro-electrodes was employed for amperometric measurement of transients and gradients with fast response time and good spatial resolution. The target analyte, hydrogen peroxide (H2O2), is the secondary species generated in enzymatic reactions (e.g. glucose with glucose oxidase), and is responsible for the redox reaction that lead to electrode current in such systems. Since the reaction constant for oxidation of H2O2 is large, the associated current response approximates the inherent response time of the sensor electrodes. In order to generate local gradients/transients, and eventually to mimic cellular function, a large platinum disk electrode (LPE) was used as a bias-controlled H2O2 sink [3], with time constants as low as 1s.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132473244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A modular spin-circuit model for magnetic tunnel junction devices 磁隧道结器件的模块化自旋电路模型
2016 74th Annual Device Research Conference (DRC) Pub Date : 2016-06-19 DOI: 10.1109/DRC.2016.7673632
Kerem Y Çamsarı, S. Ganguly, D. Datta
{"title":"A modular spin-circuit model for magnetic tunnel junction devices","authors":"Kerem Y Çamsarı, S. Ganguly, D. Datta","doi":"10.1109/DRC.2016.7673632","DOIUrl":"https://doi.org/10.1109/DRC.2016.7673632","url":null,"abstract":"We introduce a modular, physics-based, spin-circuit SPICE model to analyze conventional (charge-voltage driven) and next-generation (spin-voltage driven) Magnetic Tunnel Junctions (MTJ) in a unified circuit framework. Proposed model has 3 important novelties: (1) Quantitatively matches representative experiments for charge-driven (c-MTJ) [1,2] and spin-driven MTJ (s-MTJ) devices [3], by solving transport equations and magnetization dynamics, linking experiments directly to circuits, (2) through benchmarked circuit modules against experiments and theory [4], covers a wide range of transport and magnet phenomena, including detailed spin-transfer-torque (STT) physics at interfaces (SMR due to Giant Spin Hall Effect) [5], thermal noise in magnets, magnetic interactions between magnets as well as voltage-dependent spin-torque and TMR of MTJ devices. (3) provides circuit metrics such as Energy-Delay product [6] by capturing non-idealities including spin-absorption efficiency at the GSHE-FM interface, high-bias features of TMR and STT of the MTJs, bridging material parameters to circuit metrics. The modularity of our framework allows a \"plug-and-play\" approach to add or subtract different phenomena that are derived from a diverse set of underlying theories (spin-diffusion, quantum transport, magnetization dynamics through Landau-Lifshitz-Gilbert (LLG) equation to achieve the desired level of complexity for modeling MTJ devices. Due to these reasons, we believe our model stands out compared to others in terms of flexibility, extensibility, close connection to material parameters and depth of physics captured and is the best candidate TCAD model for the STT-MRAM industry.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130780719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Antimonide superlattice membrane detectors on a silicon substrate 硅衬底上的锑化物超晶格膜探测器
2016 74th Annual Device Research Conference (DRC) Pub Date : 2016-06-19 DOI: 10.1109/DRC.2016.7548438
M. Zamiri, B. Klein, T. Schuler, S. Myers, F. Cavallo, S. Krishna
{"title":"Antimonide superlattice membrane detectors on a silicon substrate","authors":"M. Zamiri, B. Klein, T. Schuler, S. Myers, F. Cavallo, S. Krishna","doi":"10.1109/DRC.2016.7548438","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548438","url":null,"abstract":"Wafer level integration of photonic detectors on a silicon substrate is expected to dramatically bring down the cost of detectors. State-of-the-art manufacturing of focal plane arrays (FPA) is based on wafer level processing including mesa delineation, surface passivation, metal evaporation, and indium deposition, followed by a die-level fabrication with dicing, flip-chip bonding to a silicon read-out integrated circuit, substrate thinning/removal, and packaging.i The latter steps are low-yield processesii that dramatically increase the cost and fabrication time. In the recent past, significant advancements have been made in the field of III-V materials integration onto alternate substrates, which are cheaper and easy to manufacture.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"70 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131768955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Comparison of top- and bottom-contact pentacene field-effect transistors using photocurrent microscopy 用光电流显微镜比较顶触和底触并五苯场效应晶体管
2016 74th Annual Device Research Conference (DRC) Pub Date : 2016-06-19 DOI: 10.1109/DRC.2016.7548429
A. Masurkar, I. Kymissis
{"title":"Comparison of top- and bottom-contact pentacene field-effect transistors using photocurrent microscopy","authors":"A. Masurkar, I. Kymissis","doi":"10.1109/DRC.2016.7548429","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548429","url":null,"abstract":"Overview Bottom-contact (BC) organic field-effect transistors (OFETs), though more industry-relevant than top-contact (TC) OFETs, are prone to low source-drain currents. The underlying mechanisms behind this remain debated. Thus, our work uses photocurrent microscopy (PCM) to examine charge injection in BC and TC geometries. PCM maps were generated first for OFETs with no electrode or gate dielectric treatments. Potential plots were quantitatively derived from the results using a method from previous work. [1] PCM maps were then collected for devices treated with 1. pentafluorobenzenethiol (PFBT), known to improve semiconductor morphology [2], and 2. UV-ozone, which is thought to enhance trap-assisted carrier transport. [3] These treatments were chosen, because they significantly increase source-drain current in BC devices, but in vastly different ways. In addition, unlike other photocurrent studies, we used a range of illumination wavelengths so as to probe various exciton states.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134205648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Polarization charge and coercive field dependent performance of negative capacitance FETs 负电容场效应管的极化电荷和矫顽场特性
2016 74th Annual Device Research Conference (DRC) Pub Date : 2016-06-19 DOI: 10.1109/DRC.2016.7548416
Ahmedullah Aziz, Swapnadip Ghosh, S. Gupta, S. Datta
{"title":"Polarization charge and coercive field dependent performance of negative capacitance FETs","authors":"Ahmedullah Aziz, Swapnadip Ghosh, S. Gupta, S. Datta","doi":"10.1109/DRC.2016.7548416","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548416","url":null,"abstract":"Negative capacitance FETs (NCFETs) [1, 2] have garnered an immense interest due to the possibility of achieving sub-60mV/decade sub-threshold swing at room temperature. NCFETs employ a ferroelectric (FE) material in the gate stack (Fig. 1) and utilize the negative capacitance associated with the FE to generate a voltage step up at the gate terminal, thereby achieving steep switching. In this work, we analyze the dependence of NCFET characteristics and circuit performance on the polarization charge and coercive field of FE-based gate stack through extensive experimental characterization of FE and device-circuit simulations.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"20 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134302459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Magnetoelectric device feasibility demonstration — Voltage control of exchange bias in perpendicular Cr2O3 Hall bar device 磁电装置可行性论证。垂直Cr2O3霍尔棒装置中交换偏置的电压控制
2016 74th Annual Device Research Conference (DRC) Pub Date : 2016-06-19 DOI: 10.1109/DRC.2016.7548495
Zhengyang Zhao, W. Echtenkamp, M. Street, C. Binek, Jianping Wang
{"title":"Magnetoelectric device feasibility demonstration — Voltage control of exchange bias in perpendicular Cr2O3 Hall bar device","authors":"Zhengyang Zhao, W. Echtenkamp, M. Street, C. Binek, Jianping Wang","doi":"10.1109/DRC.2016.7548495","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548495","url":null,"abstract":"Several emerging mechanisms using voltage to control the magnetism have recently been proposed because of their possible applications in energy-efficient spintronic devices [1]. Among others, one promising way to reach this goal is to use voltage to control the exchange bias of the magnetoelectric (ME) antiferromagnet Cr2O3 (Fig. 1) [2]. In this work, we demonstrate the ME effect in the device level using a bilayer thin film structure Cr2O3/[Co/Pd]n.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"61 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134258086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Fully spin-coated memory TFT 全自旋涂覆TFT存储器
2016 74th Annual Device Research Conference (DRC) Pub Date : 2016-06-19 DOI: 10.1109/DRC.2016.7548434
S. Mondal, V. Venkataraman
{"title":"Fully spin-coated memory TFT","authors":"S. Mondal, V. Venkataraman","doi":"10.1109/DRC.2016.7548434","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548434","url":null,"abstract":"The trends of recent technology are moving towards building system on panel (SOP), system on glass (SOG) or `see through' display technologies as well as towards large area flexible electronics with cost effective process[1]-[2]. Therefore the technologists are focused on developing fully spin-coated low cost sol-gel Thin Film Transistor (TFT) with solution processed Indium Gallium Zinc Oxide (IGZO) as a semiconductor[3]. It is necessary to develop transparent memory TFT by complete low cost sol-gel spin-coating technique which is suitable for large area electronics. There are several reports on transparent memory technology with IGZO as channel layer. However, most of them are fabricated with sophisticated ultra-high vacuum technique or high temperature deposition. In addition, some memory devices are only UV-erasable (not electrically) [4]. Since most of the spin-coated dielectrics are not as good as films deposited by other techniques i.e. sputtering, e-beam deposition, Atomic Layer Deposition (ALD) etc, preventing memory leakage is very difficult. Recently, we demonstrated fully spin-coated two terminal capacitive memory devices with Aluminium Oxide Phosphate (ALPO) as a dielectric and Cadmium Telluride nanoparticle (CdTe-NP) as a charge storage centre [5]. However, these structures can be useful only for SOP or SOG technology and not suitable for flexible electronics due to the high temperature processing steps. Here, we demonstrate a fully sol-gel spin-coated electrically programmable (P/E) memory three terminal TFT device (without silicon technology) with sol-gel IGZO as a deep level charge storage centre as well as channel layer. ALPO was used as tunnelling and blocking layer to prevent the memory leakage. The entire processing was carried out in the normal lab environment with the temperature processing step as low as 350°C.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117159635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Insights into interlayer tunnel FET performance improvement: Lessons learned from graphene hexagonal boron nitride heterostructures 层间隧道场效应管性能的改进:石墨烯六方氮化硼异质结构的经验教训
2016 74th Annual Device Research Conference (DRC) Pub Date : 2016-06-19 DOI: 10.1109/DRC.2016.7548442
S. Kang, N. Prasad, H. Movva, A. Rai, K. Kim, T. Taniguchi, K. Watanabe, L. F. Register, E. Tutuc, S. Banerjee
{"title":"Insights into interlayer tunnel FET performance improvement: Lessons learned from graphene hexagonal boron nitride heterostructures","authors":"S. Kang, N. Prasad, H. Movva, A. Rai, K. Kim, T. Taniguchi, K. Watanabe, L. F. Register, E. Tutuc, S. Banerjee","doi":"10.1109/DRC.2016.7548442","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548442","url":null,"abstract":"We have explored ITFETs with varying thickness of graphene conduction layers. We have found that due to the increase in the DOS for thicker graphene, the resonance peaks are enhanced. However, due to the increase in the number of sub-bands and smaller spacing between the sub-bands for multi-layer graphene, especially Bernalstacked odd number of layer graphene with Dirac cone bands, the resonance peaks are more closely spaced together and result in either subdued NDR characteristics or no NDR at all. Although an even number of layer graphene offers fewer resonance peaks, we found that for thin interlayer hBN, bandgap opening causes the peaks to broaden.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122335232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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