Antimonide superlattice membrane detectors on a silicon substrate

Abstract

Wafer level integration of photonic detectors on a silicon substrate is expected to dramatically bring down the cost of detectors. State-of-the-art manufacturing of focal plane arrays (FPA) is based on wafer level processing including mesa delineation, surface passivation, metal evaporation, and indium deposition, followed by a die-level fabrication with dicing, flip-chip bonding to a silicon read-out integrated circuit, substrate thinning/removal, and packaging.i The latter steps are low-yield processesii that dramatically increase the cost and fabrication time. In the recent past, significant advancements have been made in the field of III-V materials integration onto alternate substrates, which are cheaper and easy to manufacture.