A. West, C. Hinde, C. Messom, R. Harrison, David J. Williams
{"title":"DESIGN ISSUES ASSOCIATED WITH NEURAL NETWORK SYSTEMS APPLIED WITHIN THE ELECTRONICS MANUFACTURING DOMAIN","authors":"A. West, C. Hinde, C. Messom, R. Harrison, David J. Williams","doi":"10.1142/S0960313100000046","DOIUrl":"https://doi.org/10.1142/S0960313100000046","url":null,"abstract":"Neural networks have been applied within manufacturing domains, in particular electronics industries, to address the inherent complexity, the large number of interacting process features and the lack of robust analytical models of real industrial processes. The ability of neural systems to provide nonlinear mappings between process features and desired outputs has been the major driving force behind implementations. One of the major issues limiting the widespread industrial uptake of neural systems is the lack of detailed understanding of their design, implementation and operation. In many cases, network topologies and training parameters are systematically varied until satisfactory convergence is achieved. There is little discussion of the rationale behind the adopted training methods. A review of research into the functions that can be readily represented by neural networks are presented in this paper. The application focus is the control and monitoring of a discrete manufacturing process that is part of the manufacturing cycle of mixed technology surface mount printed circuit boards. Detailed knowledge of the process operation and functionality that can be represented by simple network topologies have been combined to develop a structured, partially interconnected neural network that provides optimised convergence performance. A comparison of the designed solution with standard approaches to neural network implementation is given. It has been demonstrated that if there is sufficient confidence in the operation of the process, input feature interaction within the network can be constrained to produce a robust control and monitoring system.","PeriodicalId":309904,"journal":{"name":"Journal of Electronics Manufacturing","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131746557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"HIGHLY ACCELERATED SOLDER JOINT RELIABILITY TEST USING A THERMO-MECHANICAL DEFLECTION SYSTEM (TMDS)","authors":"H. Pang, K. H. Ang, X. Shi, Z. Wang","doi":"10.1142/S0960313100000058","DOIUrl":"https://doi.org/10.1142/S0960313100000058","url":null,"abstract":"A Thermo-Mechanical Deflection System (TMDS) test method has been developed for evaluating the fatigue performance of solder joints in printed circuit board (PCB) assemblies. The TMDS test imparts cyclic twisting deflections on an assembled PCB test vehicle which is tested under controlled iso-thermal conditions in a thermal chamber. Tests were conducted at various angles of twist and isothermal conditions at 100°C and 25°C. Failure analysis using SEM showed that the solder joint failure for the TMDS test is comparable to the failure mechanisms for ATC test failures for solder joints. Weibull failure distribution plots for TMDS and ATC tests were compared and a Scale Factor (SF) was used to correlate the test results.","PeriodicalId":309904,"journal":{"name":"Journal of Electronics Manufacturing","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124072166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Single level integration packaging : Meeting the requirements of ultra high density and high frequency","authors":"Lirong Zheng, H. Tenhunen","doi":"10.1142/S0960313100000034","DOIUrl":"https://doi.org/10.1142/S0960313100000034","url":null,"abstract":"The traditional electronic packaging hierarchies present a bottleneck for increasing system speed and density. A revolutionary rethinking is therefore necessary which aims to integrate or eliminate the current packaging hierarchies towards single level hierarchy integration. In this paper, such a novel packaging scenario is introduced. Its technology concerns and electric performance are studied.","PeriodicalId":309904,"journal":{"name":"Journal of Electronics Manufacturing","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129492361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Lau, Chris Chang, Ricky S. W. Lee, Tsung-yuan Chen, D. Cheng, T. Tseng, D. Lin
{"title":"DESIGN AND MANUFACTURING OF MICRO VIA-IN-PAD SUBSTRATES FOR SOLDER BUMPED FLIP CHIP APPLICATIONS","authors":"J. Lau, Chris Chang, Ricky S. W. Lee, Tsung-yuan Chen, D. Cheng, T. Tseng, D. Lin","doi":"10.1142/S0960313100000101","DOIUrl":"https://doi.org/10.1142/S0960313100000101","url":null,"abstract":"A novel and low-cost micro via-in-pad (VIP) substrate for supporting a solder bumped flip chip is presented in this study. Emphasis is placed on the design, materials, process, manufacturing, and reliability of the micro VIP substrate of a chip scale package (CSP), and of the micro VIP CSP printed circuit board (PCB) assembly. Cross-sections of samples are examined for a better understanding of the solder bump, CSP redistribution, VIP, and solder joint. Non-linear finite element analyses are used to determine the stress and strain in the copper VIP and the solder joint. Time-dependent non-linear analysis is used to predict the thermal-fatigue life of the VIP solder joint.","PeriodicalId":309904,"journal":{"name":"Journal of Electronics Manufacturing","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132995411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"INTERDIGITATED CAPACITORS BY OFFSET LITHOGRAPHY","authors":"P. Harrey, P. Evans, B. Ramsey, D. Harrison","doi":"10.1142/S096031310000006X","DOIUrl":"https://doi.org/10.1142/S096031310000006X","url":null,"abstract":"This paper reports on an initial investigation into interdigitated capacitors manufactured via the offset lithographic printing process. Results taken from print-trials reveal the relationship between electrode geometry and capacitance. The paper also identifies a relationship between the substrate characteristics and the behaviour of the capacitive structures. This work is in support of a low cost and low environmental impact approach to circuit board manufacture.","PeriodicalId":309904,"journal":{"name":"Journal of Electronics Manufacturing","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122537699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"INTELLIGENT SIMULATION ENVIRONMENT FOR PRINTED CIRCUIT BOARD ASSEMBLY","authors":"S. A. Ali, Robert de Souza, Arun Kumar","doi":"10.1142/S0960313199000222","DOIUrl":"https://doi.org/10.1142/S0960313199000222","url":null,"abstract":"To provide an environment where a user can build up realistic models to identify bottlenecks, analyze the assembly line to enhance system performance in terms of productivity, queues, and cycle times as well as lead times are important areas for today's electronics manufacturing. A newly designed and developed simulation template for modeling of electronics manufacturing by using the latest achievement in object-oriented simulation software Arena is presented. The intelligent based dynamic machine knowledge, which can capture dynamic based activities using fuzzy system is also developed. The designed PCB template shows a high flexibility and good performance at an internal supply chain level and self-development, which are user-friendly. This study shows how modeling and simulation tools can be used and integrated to implement highly automated systems for industrial process in which we deal flexible product. In such context, a software prototype for the PCB with dynamic and static behavior of the material is designed and the approach is presented with real life applications, which are developed in the electronic industries of Singapore.","PeriodicalId":309904,"journal":{"name":"Journal of Electronics Manufacturing","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133334175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"THERMAL DESIGN OF HIGH POWER SEMICONDUCTOR PACKAGES FOR AIRCRAFT SYSTEMS","authors":"F. Sarvar, D. Whalley","doi":"10.1142/S0960313199000180","DOIUrl":"https://doi.org/10.1142/S0960313199000180","url":null,"abstract":"Future aircraft containing a greater proportion of electrical systems will require more extensive use of power electronics, for which thermal management is a key issue. This paper will present an approach to semiconductor package design incorporating integrated air cooled heatsinks. The paper will show how simple models of the heat transfer from heatsink fins, which are based on well established empirical correlations, may be utilised in combination with simple models of the heat conduction from the semiconductor die through the multilayer package structure to the base of the fins. These models allow the generation of design curves which may be used to rapidly explore a wide range of design options before selecting potential designs for more detailed evaluation using 3-D FE analysis. This approach has been used to design a semiconductor package for a power converter where the semiconductor devices are switched at high frequency to ensure good input and output current waveforms. The power dissipated in the semiconductors, and therefore the heatsink weight however increases with the switching frequency, whereas the associated filtering components will be smaller and lighter at higher frequencies. The optimisation of the overall system weight therefore involves a trade-off between the heatsinking and filtering requirements rather than just determining the optimum heatsink design for a specific power dissipation.","PeriodicalId":309904,"journal":{"name":"Journal of Electronics Manufacturing","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133414839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"ON SOLVING SINGLE MACHINE OPTIMIZATION PROBLEMS IN ELECTRONICS ASSEMBLY","authors":"G. Magyar, M. Johnsson, O. Nevalainen","doi":"10.1142/S0960313199000179","DOIUrl":"https://doi.org/10.1142/S0960313199000179","url":null,"abstract":"This paper deals with optimization problems arising in printed circuit board (PCB) assembly. Today's automated manufacturing systems involve a large variety of special purpose robots that together form the production line. The organization of the production includes several problems to be solved, starting from top-level tactical decisions at scheduling, through product grouping and line balancing, to single machine optimization problems. The paper deals on the single machine optimization: determining the order of component insertions and scheduling the assignment of different nozzles (tools) to the printing heads. The aim is to maximize the throughput of the machine. The machine type considered is the general surface mounting (GSM) machine. The problem is solved by modeling the production situation and the machine, decomposing the arising optimization problems into hierarchical levels, and developing effective heuristics for solving them. The practical results of the new optimizing system show significant increase (5–10%) in the productivity when compared to the current state.","PeriodicalId":309904,"journal":{"name":"Journal of Electronics Manufacturing","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125794723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Lau, Chris Chang, Tony Chen, Tsung-yuan Chen, T. Tseng, D. Cheng
{"title":"DESIGN, MANUFACTURING, AND TESTING OF A NOVEL PLASTIC BALL GRID ARRAY PACKAGE","authors":"J. Lau, Chris Chang, Tony Chen, Tsung-yuan Chen, T. Tseng, D. Cheng","doi":"10.1142/S0960313199000209","DOIUrl":"https://doi.org/10.1142/S0960313199000209","url":null,"abstract":"The design, manufacturing, analysis, and measurement of a thermal and electrical enhanced cavity-down plastic ball grid array (PBGA) package are presented in this study. Because of the split via connection (SVC) design, the package consists of a very-thin single core of organic material and two-metal layers of copper and is manufactured with the conventional printed circuit board (PCB) process at very low cost. Furthermore, the heat spreader is made with bottom surface having saw-teeth to contact the ground planes disposed on the backside of the substrate. Improvements in electrical and thermal performance are achieved. Parasitic parameters of the package are extracted from time domain reflectometer (TDR) measurements. The thermal performances of the packages are studied by both 3D finite element analysis and wind-tunnel measurements. The results are compared with other well-known packages.","PeriodicalId":309904,"journal":{"name":"Journal of Electronics Manufacturing","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123490227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"ELECTROMAGNETIC WAVE TRANSMISSION THROUGH LOSSLESS ELECTRICALLY CONDUCTIVE ADHESIVE","authors":"Y. Fu, Johan Liu, M. Willander","doi":"10.1142/S0960313199000192","DOIUrl":"https://doi.org/10.1142/S0960313199000192","url":null,"abstract":"We report our theoretical study on the electric conduction and the electromagnetic wave transmission between the IC chip and the substrate. The IC chip and the substrate are connected electrically by upper and lower contact shoulders which are conductively connected through an anisotropically conductive adhesive (ACA). It has been concluded that following the increase of the frequency of the electromagnetic field, the transmission of the electromagnetic field shifts from the conducting medium (metal) to non-conducting medium (adhesive) due to the skin effect. The DC electric conduction of the ACA is limited by the sizes, geometric shapes as well as spatial positions of metal fillers in the ACA. By excluding energy dissipation processes (because of the short distance between the upper and the lower contacts), our theoretical simulation indicates that the transmission of high-frequency (above 1 GHz when discussing the conduction properties of metal fillers having radius of no less than 5 μm) electromagnetic wave through the ACA is almost independent of the metal fillers because of the displacement current in the non-conductive medium between the upper and lower contacts.","PeriodicalId":309904,"journal":{"name":"Journal of Electronics Manufacturing","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127458433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}