DESIGN AND MANUFACTURING OF MICRO VIA-IN-PAD SUBSTRATES FOR SOLDER BUMPED FLIP CHIP APPLICATIONS

Abstract

A novel and low-cost micro via-in-pad (VIP) substrate for supporting a solder bumped flip chip is presented in this study. Emphasis is placed on the design, materials, process, manufacturing, and reliability of the micro VIP substrate of a chip scale package (CSP), and of the micro VIP CSP printed circuit board (PCB) assembly. Cross-sections of samples are examined for a better understanding of the solder bump, CSP redistribution, VIP, and solder joint. Non-linear finite element analyses are used to determine the stress and strain in the copper VIP and the solder joint. Time-dependent non-linear analysis is used to predict the thermal-fatigue life of the VIP solder joint.