Nabil El Belghiti Alaoui, Patrick Tounsi, A. Boyer, A. Viard
{"title":"Detecting PCB Assembly Defects Using Infrared Thermal Signatures","authors":"Nabil El Belghiti Alaoui, Patrick Tounsi, A. Boyer, A. Viard","doi":"10.23919/MIXDES.2019.8787089","DOIUrl":"https://doi.org/10.23919/MIXDES.2019.8787089","url":null,"abstract":"A Printed Circuit Board assembly (PCBA) testing approach using infrared thermal signatures is presented. The concept of thermal signature for PCBAs is introduced. Based on this concept, the testing method is able to: - detect assembly defects such as presence, polarity, value and solder (shorts and opens) and in some cases component health state - classify the components mounted on the PCB into a number of classes (e.g. – fault free(reliable), functional (less reliable), faulty ). According to the thermal signature of each component on the PCBA, PCBAs can be also classified in the same number of classes. In this article a special focus is put on capacitor defects especially capacitor value defects. Therefore, they will be the main components tested. The fault detection indicator used in this proof of concept is a statistical mean squared error measure (MSE).","PeriodicalId":309822,"journal":{"name":"2019 MIXDES - 26th International Conference \"Mixed Design of Integrated Circuits and Systems\"","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114520102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sara Ghafari, Morteza Mousazadeh, A. Khoei, A. Dadashi
{"title":"A New Very High-speed True 7-3 Compressor","authors":"Sara Ghafari, Morteza Mousazadeh, A. Khoei, A. Dadashi","doi":"10.23919/MIXDES.2019.8787157","DOIUrl":"https://doi.org/10.23919/MIXDES.2019.8787157","url":null,"abstract":"In this paper, a new high-speed 7-3 compressor for high-speed arithmetic operations is presented. This compressor takes advantage of the current-mode techniques, also inverter gate’s property, especially back to back inverters to achieve the minimum delay. The proposed architecture is an altered size of the input number compressor. This feature will be important when 4, 5 or 6 partial product bits exist to compress in Multiplier, which can reduce the extra area and power. All the proposed designs are evaluated by exhaustive HSPICE simulations in 0.18um standard CMOS technology with 0.18V power supply voltage and supplementary simulation have been done to examine the effect of terms. The results show performance improvements with more than 3 times higher speed and 18 percent lower PDP compared to the purely digital design.","PeriodicalId":309822,"journal":{"name":"2019 MIXDES - 26th International Conference \"Mixed Design of Integrated Circuits and Systems\"","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115269650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Implementation of an I2C to Profibus Serial Comunication Interface","authors":"T. P. Mussolini, F. Ramos, R. Moreno, T. Pimenta","doi":"10.23919/MIXDES.2019.8787091","DOIUrl":"https://doi.org/10.23919/MIXDES.2019.8787091","url":null,"abstract":"This work proposes a PROFIBUS peripheral device that can provide interface to CPU/MCU. The implemented circuit satisfies the high performance requirements of equipment for industrial networks, according to IEC 61158-2. The circuit consists of Manchester encoder/decoder, time-critical hardware timers and other functions necessary to implement the data link layer for industrial networks using PROFIBUS-PA protocols. The communication between the CPU/MPU and the proposed device is conducted on I2C serial communication standard. This paper describes the protocols used to read/write commands and data on the device. The circuit was validated on FPGA and can be used as an alternative to commercial models that work with the old parallel ports that are leaving the market.","PeriodicalId":309822,"journal":{"name":"2019 MIXDES - 26th International Conference \"Mixed Design of Integrated Circuits and Systems\"","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123448119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 4.5 fJ/conversion-step 10-bit 0.6V Asynchronous SAR ADC for Battery-free Miniature Sensor Nodes in 65nm CMOS","authors":"A. Dadashi, Y. Berg, O. Mirmotahari","doi":"10.23919/MIXDES.2019.8787150","DOIUrl":"https://doi.org/10.23919/MIXDES.2019.8787150","url":null,"abstract":"This paper presents a 0.6-V energy-efficient 10-bit Asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with internal clock generator. Also a multiplexer is designed to serially transfer the output bits to outside the chip. A novel capacitive array also is proposed in this paper. The prototype is designed and fabricated in a 65-nm CMOS with a core size of 290 μm × 130 pm (0.0377 mm2). At 2.4 KS/s and Nyquist rate input, it consumes 4 nW at 0.6-V supply with an achieved signal-to-noise-and distortion ratio of 53.2 dB and a resulting figure of merit (FOM) of 4.5 fJ/conv.-step. Prototyped in a low-power 65 nm CMOS process, the ADC achieves an INL and DNL of 1.57 LSB and 0.95 LSB respectively at 0.6 V supply.","PeriodicalId":309822,"journal":{"name":"2019 MIXDES - 26th International Conference \"Mixed Design of Integrated Circuits and Systems\"","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126757859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Continuous-Time Discriminator Design in CMOS 28 nm Process","authors":"P. Kaczmarczyk, P. Kmon","doi":"10.23919/MIXDES.2019.8787153","DOIUrl":"https://doi.org/10.23919/MIXDES.2019.8787153","url":null,"abstract":"This paper presents the discriminator design in 28 nm CMOS process. The core of the discriminator is based on the Operational Transconductance Amplifier (OTA) supported by additional blocks for its main parameters improvement. The positive feedback and Negative Impedance Converter (NIC) have been verified and are presented hereby. The article provides information on how particular improvement blocks influence the discriminator operation speed, its power consumption and area occupation. Finally, the proposed new architecture shows more than six times speed improvement while consuming only 31% more power compared to the standard discriminator architecture. Additionally, the proposed solution mitigates the problem of the discriminator’s time response susceptibility on the input signal level. The final circuit consumes 3.8 μW of power at 10 MHz operating frequency, occupies only a 15 μm2 of area and allows to operate with impulses of 1.25 GHz frequency.","PeriodicalId":309822,"journal":{"name":"2019 MIXDES - 26th International Conference \"Mixed Design of Integrated Circuits and Systems\"","volume":"40 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126856381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Non-disjoint Decomposition Using r-admissibility and Graph Coloring and Its Application in Index Generation Functions Minimization","authors":"T. Mazurkiewicz, T. Luba","doi":"10.23919/MIXDES.2019.8787118","DOIUrl":"https://doi.org/10.23919/MIXDES.2019.8787118","url":null,"abstract":"Functional decomposition is a crucial task in logic synthesis. In this paper we present a theory for finding such decomposition using the notion of r-admissibility and graph coloring. In particular, a method for generating the set of bound variables in the non-disjoint scheme is presented. We present the results of experiments, which apply proposed algorithm to minimize specific Boolean functions called index generation functions. In this way we prove that functional decomposition can efficiently reduce the size of used memory in memory-based logic synthesis.","PeriodicalId":309822,"journal":{"name":"2019 MIXDES - 26th International Conference \"Mixed Design of Integrated Circuits and Systems\"","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129881341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Oleksiak, Sebastian Cieslak, Krzysztof Marcinek, W. Pleskacz
{"title":"Design and Verification Environment for RISC-V Processor Cores","authors":"A. Oleksiak, Sebastian Cieslak, Krzysztof Marcinek, W. Pleskacz","doi":"10.23919/MIXDES.2019.8787108","DOIUrl":"https://doi.org/10.23919/MIXDES.2019.8787108","url":null,"abstract":"Processor verification is a very complex task. Even simple system has plenty of blocks which must work together in a determined way. Modern digital systems use advanced techniques to improve throughput and reduce power consumption. It enhances risk of error and consequently verification process requires a significant and continuous resources. This article presents the approach to create design and verification environment for RISC-V processor cores. The environment consists of behavioral golden reference model and online disassembler module, as well as a set of scripts for setting up software infrastructure. Golden reference model running in master-checker mode with core under design allows faulty behavior to be detected instantly while running direct tests or random verification technique.","PeriodicalId":309822,"journal":{"name":"2019 MIXDES - 26th International Conference \"Mixed Design of Integrated Circuits and Systems\"","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129310043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analysis and Modelling of ICs and Microsystems","authors":"","doi":"10.23919/mixdes.2019.8787165","DOIUrl":"https://doi.org/10.23919/mixdes.2019.8787165","url":null,"abstract":"","PeriodicalId":309822,"journal":{"name":"2019 MIXDES - 26th International Conference \"Mixed Design of Integrated Circuits and Systems\"","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116349876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
O. Matviykiv, N. Bokla, T. Klymkovych, U. Marikutsa, I. Farmaha, M. Lobur, M. Banaś
{"title":"Lab-chip Diagnostic Device for the Rainwater Monitoring System Using Wireless Sensors Network","authors":"O. Matviykiv, N. Bokla, T. Klymkovych, U. Marikutsa, I. Farmaha, M. Lobur, M. Banaś","doi":"10.23919/MIXDES.2019.8787185","DOIUrl":"https://doi.org/10.23919/MIXDES.2019.8787185","url":null,"abstract":"The research article addressed the problem of developing rainwater quality monitoring system based on movable WSN nodes for detection hazardous environmental pollutions. The focus of the monitoring system was pointed on the network layer design with movable WSN nodes (monitoring stations). Pressure, temperature, air pollutions and rainwater contaminants are collected by sensor nodes, which permanently moves on various platforms, and then transmitted to an intermediate hub and further to central server for precise processing. Proposed monitoring system allows to explore and control the environmental air/rainwater parameters at various remote locations of environmentally hazardous cities and regions. Explore the environmental hazards that might be found at various locations within cities and towns,","PeriodicalId":309822,"journal":{"name":"2019 MIXDES - 26th International Conference \"Mixed Design of Integrated Circuits and Systems\"","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132317309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Sobotnicka, A. Sobotnicki, Marek Czerw, G. Badura, M. Krej, L. Puchalska, Krzystof Kowalczuk, S. Gaździński, L. Dziuda
{"title":"Methods to Assess Self-regulatory Mechanisms of the Cardiovascular System under Simulated Hypergravity Conditions","authors":"E. Sobotnicka, A. Sobotnicki, Marek Czerw, G. Badura, M. Krej, L. Puchalska, Krzystof Kowalczuk, S. Gaździński, L. Dziuda","doi":"10.23919/MIXDES.2019.8787152","DOIUrl":"https://doi.org/10.23919/MIXDES.2019.8787152","url":null,"abstract":"The paper presents essential methods which enable the assessment of self-regulatory mechanisms of the cardiovascular system under simulated hypergravity conditions deployed in tests for pilots. The following testing procedures have been discussed: generating lower body negative pressure (LBNP) and positive pressure (LBPP), a head upright tilt table test (HUT), a head-down tilt (HDT) and Push-Pull mechanism. The paper also describes examples of solutions intended to simulate hypergravity conditions with particular emphasis on ORTO-LBNP, an original system used in tests for pilots and aviation candidates. The designed system is equipped with specially suited measurement modules to record physiological parameters, with a focus on cardiovascular system parameters. The developed dedicated measurement modules can be placed in one measurement cartridge, and thus can be used continuously during the test with the use of the ORTO-LBNP stand, in this way making it possible to perform both the orthostatic and LBNP test at the same time and to continuously record the physiological parameters. The paper also features preliminary results obtained during the operation of the measurement module used for the acquisition of bioimpedance signals from the thorax.","PeriodicalId":309822,"journal":{"name":"2019 MIXDES - 26th International Conference \"Mixed Design of Integrated Circuits and Systems\"","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130005367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}