2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems"最新文献

Stage-oriented, Mixed Design Methodology for Image Processing Using VHDL and Python 基于VHDL和Python的面向阶段、混合设计的图像处理方法

2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems" Pub Date : 2019-06-27 DOI: 10.23919/MIXDES.2019.8787204

Marcin Chojnacki, P. Sekalski

{"title":"Stage-oriented, Mixed Design Methodology for Image Processing Using VHDL and Python","authors":"Marcin Chojnacki, P. Sekalski","doi":"10.23919/MIXDES.2019.8787204","DOIUrl":"https://doi.org/10.23919/MIXDES.2019.8787204","url":null,"abstract":"The data analysis could be a very time consuming process during the hardware design on FPGA platforms. The verification process of designed modules is important at each step of a design process. In some cases standard methods for data analysis are insufficient, especially when the data representation are taken into assessment methods. In image processing systems based on FPGA there are various methods to support engineers in development of desired architecture. Some of them are based on scoping hardware signals in running device. It is also possible to scope signals in a simulation environment. In addition there are also high-level abstraction layer of data analysis methods based on Matlab, Python and similar tools. The unique image processing architecture developed by authors could not be upgraded with support of existing co-design methods. This is why stage-oriented, mixed design methodology was performed to support FPGA hardware development for faster prototyping and debugging with Vivado simulator tool and Python language. Presented approach was used to improve image processing design operating with ultra high resolution images (from 5 Mpix up to 70 Mpix).","PeriodicalId":309822,"journal":{"name":"2019 MIXDES - 26th International Conference \"Mixed Design of Integrated Circuits and Systems\"","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115116161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Improving Dual-Slope A/D Converter with Noise-Shaping and Digital Filtering Techniques 用噪声整形和数字滤波技术改进双斜率A/D转换器

2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems" Pub Date : 2019-06-27 DOI: 10.23919/MIXDES.2019.8787142

P. Sniatala, D. Makowski, J. Goes, W. Machowski, Sergio Salas Arriarán

引用次数: 0

Semiconductor Device Parameter Extraction Based on I–V Measurements and Simulation 基于I-V测量的半导体器件参数提取与仿真

2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems" Pub Date : 2019-06-27 DOI: 10.23919/MIXDES.2019.8787195

D. Kasprowicz

引用次数: 1

Characterization of the Charge-Trap Dynamics in Organic Thin-Film Transistors 有机薄膜晶体管中电荷阱动力学的表征

2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems" Pub Date : 2019-06-27 DOI: 10.23919/MIXDES.2019.8787105

G. Darbandy, C. Roemer, Jakob Leise, Jakob Pruefer, James W. Borchert, H. Klauk, A. Kloes

引用次数: 7

Closed-Form Modeling Approach of Trap-Assisted Tunneling Current for Use in Compact TFET Models 用于紧凑ttfet模型的陷阱辅助隧道电流封闭建模方法

2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems" Pub Date : 2019-06-27 DOI: 10.23919/MIXDES.2019.8787095

F. Horst, A. Farokhnejad, B. Iñíguez, A. Kloes

{"title":"Closed-Form Modeling Approach of Trap-Assisted Tunneling Current for Use in Compact TFET Models","authors":"F. Horst, A. Farokhnejad, B. Iñíguez, A. Kloes","doi":"10.23919/MIXDES.2019.8787095","DOIUrl":"https://doi.org/10.23919/MIXDES.2019.8787095","url":null,"abstract":"This paper presents a novel compact modeling approach to consider the effect of trap-assisted tunneling (TAT) in the calculations of the tunneling current in tunnel field-effect transistors (TFETs). The closed-form and physics-based model equations are implemented in the hardware description language Verilog-A and thus extend an existing model for the B2B tunneling current calculation in double-gate (DG) TFETs.In order to verify the modeling approach, simulation results are compared to TCAD Sentaurus simulations. The compact model shows a good fit in the current transfer curves for various drain-source voltages, trap densities, drain doping concentrations and different source materials. The current output curve and the output conductance stay also in good agreement with TCAD data. In the next step, the compact model is verified with the help of measurements of fabricated complementary TFET devices. During the verification process, limitations and advantages of the modeling approach are analyzed and discussed. The influence of TAT on a fabricated single-stage TFET inverter is investigated in a last verification step, whereby the numerical stability and flexibility of the model is demonstrated.","PeriodicalId":309822,"journal":{"name":"2019 MIXDES - 26th International Conference \"Mixed Design of Integrated Circuits and Systems\"","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117327959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A Review on Quantum Computing: From Qubits to Front-end Electronics and Cryogenic MOSFET Physics 量子计算综述:从量子比特到前端电子学和低温MOSFET物理

2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems" Pub Date : 2019-06-27 DOI: 10.23919/MIXDES.2019.8787164

F. Jazaeri, A. Beckers, A. Tajalli, J. Sallese

引用次数: 48

Novel Design Solution of Reconnection-less Electronically Reconfigurable Filter 无重接电子可重构滤波器的新设计方案

2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems" Pub Date : 2019-06-27 DOI: 10.23919/MIXDES.2019.8787140

L. Langhammer, R. Sotner, Jan Dvorak, T. Dostál

引用次数: 2

Wireless System for Diagnostics of Wound Healing 无线伤口愈合诊断系统

2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems" Pub Date : 2019-06-27 DOI: 10.23919/MIXDES.2019.8787124

D. Obrebski, M. Zbiec, A. Pepłowski, D. Janczak, M. Zych, M. Jakubowska

引用次数: 0

Analytical Model for Threshold-Voltage Shift in Submicron Staggered Organic Thin-Film Transistors 亚微米交错有机薄膜晶体管阈值-电压位移的解析模型

2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems" Pub Date : 2019-06-27 DOI: 10.23919/MIXDES.2019.8787083

Jakob Prüfer, Jakob Leise, G. Darbandy, James W. Borchert, H. Klauk, B. Iñíguez, T. Gneiting, A. Kloes

引用次数: 2

What is Killing Moore's Law? Challenges in Advanced FinFET Technology Integration 什么是杀死摩尔定律?先进FinFET技术集成的挑战

2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems" Pub Date : 2019-06-27 DOI: 10.23919/MIXDES.2019.8787084

A. Malinowski, James Chen, S. Mishra, S. Samavedam, D. K. Sohn

{"title":"What is Killing Moore's Law? Challenges in Advanced FinFET Technology Integration","authors":"A. Malinowski, James Chen, S. Mishra, S. Samavedam, D. K. Sohn","doi":"10.23919/MIXDES.2019.8787084","DOIUrl":"https://doi.org/10.23919/MIXDES.2019.8787084","url":null,"abstract":"First microprocessor released to the market in 1971 was consisting of 2300 transistors. Following Moore's law less than five decades later consumer electronic chips consist of billions of transistor reaching densities as much as 100 million transistors in square millimeter Several times in the past it was predicted that technological barriers would slow or even stop CMOS technology scaling trend. Despite these predictions, the monetary benefit of growth has been driving massive research and pathways have been Lays found around those barriers. In 2011 a 3-D tri-gate transistor structure, FinFET, has been introduced into CMOS mainstream manufacturing which was a pathway replacing running out of steam planar technology. However, similarly to the planar technology now FinFET scaling is running out of steam due to difficult technological barriers and integration challenges. In 2021 year last CMOS technology node based on FinFET might be released for production. Difficulties and technology integration challenges outlined in this paper may end 10-year era of FinFET technology.","PeriodicalId":309822,"journal":{"name":"2019 MIXDES - 26th International Conference \"Mixed Design of Integrated Circuits and Systems\"","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132701419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9