Characterization of the Charge-Trap Dynamics in Organic Thin-Film Transistors

Abstract

Step and pulse response transient measurements are performed in organic TFTs to study the charge trapping, detrapping dynamics and DC gate/drain bias stress effects on device characteristics. A strong correlation has been demonstrated between the device performance and bias stress effect. The measurement procedure must be carefully set up to analyze the dynamic channel response and the consistent/actual extraction of the device figures of merit (threshold voltage, on/off current ratio, contact resistance, transit frequency, etc). Device operation and bias conditions, historical stress (prefilled traps) and the impact of charge traps can have a strong influence on the device characteristics and their applications due to the affected device DC/AC parameters. The decrease/increase of the drain current when the biases are applied is associated to the effect of charge trapping/detrapping.