Continuous-Time Discriminator Design in CMOS 28 nm Process

This paper presents the discriminator design in 28 nm CMOS process. The core of the discriminator is based on the Operational Transconductance Amplifier (OTA) supported by additional blocks for its main parameters improvement. The positive feedback and Negative Impedance Converter (NIC) have been verified and are presented hereby. The article provides information on how particular improvement blocks influence the discriminator operation speed, its power consumption and area occupation. Finally, the proposed new architecture shows more than six times speed improvement while consuming only 31% more power compared to the standard discriminator architecture. Additionally, the proposed solution mitigates the problem of the discriminator’s time response susceptibility on the input signal level. The final circuit consumes 3.8 μW of power at 10 MHz operating frequency, occupies only a 15 μm2 of area and allows to operate with impulses of 1.25 GHz frequency.