Design and Verification Environment for RISC-V Processor Cores

Abstract

Processor verification is a very complex task. Even simple system has plenty of blocks which must work together in a determined way. Modern digital systems use advanced techniques to improve throughput and reduce power consumption. It enhances risk of error and consequently verification process requires a significant and continuous resources. This article presents the approach to create design and verification environment for RISC-V processor cores. The environment consists of behavioral golden reference model and online disassembler module, as well as a set of scripts for setting up software infrastructure. Golden reference model running in master-checker mode with core under design allows faulty behavior to be detected instantly while running direct tests or random verification technique.